RT-Thread-STM32H743+LAN8720A的ETH驱动详细讲解RT-Thread问答社区

STM32H743+LAN8720A的ETH驱动详细讲解

发布于 2024-08-07 11:35:44 浏览：1256 订阅该版

[tocm]

## 一、根据原理图，使用STM32CUBEMX生成IO初始化代码
### 1.查看原理图
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/5cdf604229dd86a3d5d532c71b99ac5f.png.webp)
### 2.根据原理图的引脚连接定义成基础代码
2.1P配置RMII引脚
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/07f3a001dc35958905a089efbde4760d.png.webp)
2.2配置时钟
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/297df77ac401fdc1c5ec15fb38be0f32.png.webp)
配置HSE为25Mhz（我的板子上是25M），时钟频率直接拉到480Mhz，然后点击确认，他会自动计算各个参时钟参数的
2.3生成代码
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/99c5419cc4181919de6d28f2a7be0eb1.png.webp)
## 二、使用rtthread studio生成初始化代码，版本选rtthread v4.1.1
1.利用studio生成基础代码
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/3c2da0dd9d694ab3dbf601efaca914c7.png)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/ee88abb43a0f0046bfb03eabd8e760f1.png)
## 三、复制时钟函数和xxx_msp初始化的函数到board.c文件中，修改board.h文件中的配置参数
1.复制时钟函数到drv_clk.c中
```c
void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

/** Supply configuration update enable
  */
  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 5;
  RCC_OscInitStruct.PLL.PLLN = 192;
  RCC_OscInitStruct.PLL.PLLP = 2;
  RCC_OscInitStruct.PLL.PLLQ = 2;
  RCC_OscInitStruct.PLL.PLLR = 2;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }
}
```
2.修改时钟函数

```c
void clk_init(char *clk_source, int source_freq, int target_freq)
{
    /*
     * Use SystemClock_Config generated from STM32CubeMX for clock init
     * system_clock_config(target_freq);
     */
    extern void SystemClock_Config(void);
    SystemClock_Config();
}
```
3.复制RMII的初始化代码到board.c中
```c
void HAL_MspInit(void)
{
  /* USER CODE BEGIN MspInit 0 */

/* USER CODE END MspInit 0 */

__HAL_RCC_SYSCFG_CLK_ENABLE();

HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);

/* System interrupt init*/
  /* MemoryManagement_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
  /* BusFault_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
  /* UsageFault_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
  /* SVCall_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
  /* DebugMonitor_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0);
  /* SysTick_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);

/* USER CODE BEGIN MspInit 1 */

/* USER CODE END MspInit 1 */
}

void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
    GPIO_InitTypeDef GPIO_InitStruct = { 0 };
    if (heth->Instance == ETH)
    {
        /* USER CODE BEGIN ETH_MspInit 0 */

/* USER CODE END ETH_MspInit 0 */
        /* Peripheral clock enable */
        __HAL_RCC_ETH1MAC_CLK_ENABLE()
        ;
        __HAL_RCC_ETH1TX_CLK_ENABLE()
        ;
        __HAL_RCC_ETH1RX_CLK_ENABLE()
        ;

__HAL_RCC_GPIOC_CLK_ENABLE()
        ;
        __HAL_RCC_GPIOA_CLK_ENABLE()
        ;
        __HAL_RCC_GPIOG_CLK_ENABLE()
        ;
        /**ETH GPIO Configuration
         PC1     ------> ETH_MDC
         PA1     ------> ETH_REF_CLK
         PA2     ------> ETH_MDIO
         PA7     ------> ETH_CRS_DV
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         PG11     ------> ETH_TX_EN
         PG12     ------> ETH_TXD1
         PG13     ------> ETH_TXD0
         */
        GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
        GPIO_InitStruct.Pull = GPIO_NOPULL;
        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
        GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
        HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
        GPIO_InitStruct.Pull = GPIO_NOPULL;
        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
        GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
        GPIO_InitStruct.Pull = GPIO_NOPULL;
        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
        GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
        HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);

/* USER CODE BEGIN ETH_MspInit 1 */
        HAL_NVIC_SetPriority(ETH_IRQn,1,0);         //网络中断优先级应该高一点
        HAL_NVIC_EnableIRQ(ETH_IRQn);
        /* USER CODE END ETH_MspInit 1 */
    }

}

/**
 * @brief ETH MSP De-Initialization
 * This function freeze the hardware resources used in this example
 * @param heth: ETH handle pointer
 * @retval None
 */
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
{
    if (heth->Instance == ETH)
    {
        /* USER CODE BEGIN ETH_MspDeInit 0 */

/* USER CODE END ETH_MspDeInit 0 */
        /* Peripheral clock disable */
        __HAL_RCC_ETH1MAC_CLK_DISABLE();
        __HAL_RCC_ETH1TX_CLK_DISABLE();
        __HAL_RCC_ETH1RX_CLK_DISABLE();

/**ETH GPIO Configuration
         PC1     ------> ETH_MDC
         PA1     ------> ETH_REF_CLK
         PA2     ------> ETH_MDIO
         PA7     ------> ETH_CRS_DV
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         PG11     ------> ETH_TX_EN
         PG12     ------> ETH_TXD1
         PG13     ------> ETH_TXD0
         */
        HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);

HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);

HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13);

/* USER CODE BEGIN ETH_MspDeInit 1 */

/* USER CODE END ETH_MspDeInit 1 */
    }

}
```
4.编写mpu_config函数到board.c中

```c
/**
  * 函数功能: 设置网络所使用的0X30040000的ram内存保护
  * 输入参数: 无
  * 返 回 值: 无
  * 说    明: 无
  */
void MPU_Config(void)
{
    MPU_Region_InitTypeDef MPU_InitStruct={0};

HAL_MPU_Disable();
    MPU_InitStruct.Enable=MPU_REGION_ENABLE;
    MPU_InitStruct.BaseAddress=0x30040000;
    MPU_InitStruct.Size=MPU_REGION_SIZE_256B;
    MPU_InitStruct.AccessPermission=MPU_REGION_FULL_ACCESS;
    MPU_InitStruct.IsBufferable=MPU_ACCESS_BUFFERABLE;
    MPU_InitStruct.IsCacheable=MPU_ACCESS_NOT_CACHEABLE;
    MPU_InitStruct.IsShareable=MPU_ACCESS_SHAREABLE;
    MPU_InitStruct.Number=MPU_REGION_NUMBER5;
    MPU_InitStruct.TypeExtField=MPU_TEX_LEVEL0;
    MPU_InitStruct.SubRegionDisable=0x00;
    MPU_InitStruct.DisableExec=MPU_INSTRUCTION_ACCESS_ENABLE;
    HAL_MPU_ConfigRegion(&MPU_InitStruct);
    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

}
```
## 四、替换driver驱动中的drv_eth.c和drv_eth.h
1.此处参考论坛的驱动代码，替换自动生成的drv_eth.c和drv_eth.h
此处加了一点自己的修改部分
```c
/*
 * Copyright (c) 2006-2018, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2018-11-19     SummerGift   first version
 * 2018-12-25     zylx         fix some bugs
 * 2019-06-10     SummerGift   optimize PHY state detection process
 * 2019-09-03     xiaofan      optimize link change detection process
 * 2020-07-17     wanghaijing  support h7
 * 2020-11-30     wanghaijing  add phy reset
 */

#include<rtthread.h>
#include<rtdevice.h>
#include "board.h"
#include "drv_config.h"

#ifdef BSP_USING_ETH

#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "drv_eth.h"

/*
* Emac driver uses CubeMX tool to generate emac and phy's configuration,
* the configuration files can be found in CubeMX_Config folder.
*/

/* debug option */
//#define ETH_RX_DUMP
//#define ETH_TX_DUMP
//#define DRV_DEBUG
#define LOG_TAG             "drv.emac"
#include <drv_log.h>

#define MAX_ADDR_LEN 6

struct rt_stm32_eth
{
    /* inherit from ethernet device */
    struct eth_device parent;
#ifndef PHY_USING_INTERRUPT_MODE
    rt_timer_t poll_link_timer;
#endif

/* interface address info, hw address */
    rt_uint8_t  dev_addr[MAX_ADDR_LEN];
    /* ETH_Speed */
    uint32_t    ETH_Speed;
    /* ETH_Duplex_Mode */
    uint32_t    ETH_Mode;
};

static ETH_HandleTypeDef EthHandle;
static ETH_TxPacketConfig TxConfig;
static struct rt_stm32_eth stm32_eth_device;
static uint8_t PHY_ADDR = 0x1F;
static rt_uint32_t reset_pin = 0;

#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma location=0x30040000
ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
#pragma location=0x30040060
ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
#pragma location=0x30040200
uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */

#elif defined ( __CC_ARM )  /* MDK ARM Compiler */
__attribute__((at(0x30040000))) ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
__attribute__((at(0x30040060))) ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
__attribute__((at(0x30040200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */

#elif defined ( __GNUC__ ) /* GNU Compiler */
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection")));   /* Ethernet Tx DMA Descriptors */
uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */
#endif

#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
{
    unsigned char *buf = (unsigned char *)ptr;
    int i, j;

for (i = 0; i < buflen; i += 16)
    {
        rt_kprintf("%08X: ", i);

for (j = 0; j < 16; j++)
            if (i + j < buflen)
                rt_kprintf("%02X ", buf[i + j]);
            else
                rt_kprintf("   ");
        rt_kprintf(" ");

for (j = 0; j < 16; j++)
            if (i + j < buflen)
                rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
        rt_kprintf("\n");
    }
}
#endif

static void phy_reset(void)
{
    rt_pin_write(reset_pin, PIN_LOW);
    rt_kprintf("pin_reset:%d\r\n",rt_pin_read(reset_pin));
    rt_thread_mdelay(50);
    rt_pin_write(reset_pin, PIN_HIGH);

rt_kprintf("pin_reset:%d\r\n",rt_pin_read(reset_pin));
}

/* EMAC initialization function */
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
    ETH_MACConfigTypeDef MACConf;
    uint32_t regvalue = 0;
    uint8_t  status = RT_EOK;

__HAL_RCC_D2SRAM3_CLK_ENABLE();

phy_reset();

/* ETHERNET Configuration */
    EthHandle.Instance = ETH;
    EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
    EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE;
    EthHandle.Init.TxDesc = DMATxDscrTab;
    EthHandle.Init.RxDesc = DMARxDscrTab;
    EthHandle.Init.RxBuffLen = ETH_MAX_PACKET_SIZE;

//    SCB_InvalidateDCache();

extern void MPU_Config(void);
    MPU_Config();

HAL_ETH_DeInit(&EthHandle);

/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
    if (HAL_ETH_Init(&EthHandle) != HAL_OK)
    {
        LOG_E("eth hardware init failed");
    }
    else
    {
        LOG_D("eth hardware init success");
    }

rt_memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
    TxConfig.Attributes   = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
    TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
    TxConfig.CRCPadCtrl   = ETH_CRC_PAD_INSERT;

for (int idx = 0; idx < ETH_RX_DESC_CNT; idx++)
    {
        HAL_ETH_DescAssignMemory(&EthHandle, idx, &Rx_Buff[idx][0], NULL);
    }

HAL_ETH_SetMDIOClockRange(&EthHandle);

for(int i = 0; i <= PHY_ADDR; i ++)
     {
       if(HAL_ETH_ReadPHYRegister(&EthHandle, i, PHY_SPECIAL_MODES_REG, ®value) != HAL_OK)
       {
         status = RT_ERROR;
         /* Can't read from this device address continue with next address */
         continue;
       }

if((regvalue & PHY_BASIC_STATUS_REG) == i)
       {
         PHY_ADDR = i;
         status = RT_EOK;
         LOG_D("Found a phy, address:0x%02X", PHY_ADDR);
         break;
       }
     }

if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK)
     {
         HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_SPECIAL_MODES_REG, ®value);

uint32_t tickstart = rt_tick_get();
         rt_kprintf("regvalue:0x%8x\r\n",regvalue);
         /* wait until software reset is done or timeout occured  */
         while(regvalue & PHY_RESET_MASK)
         {
           if((rt_tick_get() - tickstart) <= 1000)
           {
             if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) != HAL_OK)
             {
               status = RT_ERROR;
               rt_kprintf("phy error\r\n");
               break;
             }
           }
           else
           {
             status = RT_ETIMEOUT;
             RT_ASSERT(status!=RT_ETIMEOUT);

}
         }
     }

rt_thread_delay(2000);

if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) == HAL_OK)
     {
         regvalue |= PHY_AUTO_NEGOTIATION_MASK;
         HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, regvalue);

eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
         HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
         MACConf.DuplexMode = ETH_FULLDUPLEX_MODE;
         MACConf.Speed = ETH_SPEED_100M;
         HAL_ETH_SetMACConfig(&EthHandle, &MACConf);

HAL_ETH_Start_IT(&EthHandle);
     }
     else
     {
         status = RT_ERROR;
     }

return status;
}

static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
    LOG_D("emac open");
    return RT_EOK;
}

static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
    LOG_D("emac close");
    return RT_EOK;
}

static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
    LOG_D("emac read");
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
    LOG_D("emac write");
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
    switch (cmd)
    {
    case NIOCTL_GADDR:
        /* get mac address */
        if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
        else return -RT_ERROR;
        break;

default :
        break;
    }

return RT_EOK;
}

/* ethernet device interface */
/* transmit data*/
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
{
    rt_err_t ret = RT_ERROR;
    HAL_StatusTypeDef state;
    uint32_t i = 0, framelen = 0;
    struct pbuf *q;
    ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT];

rt_memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef));

for (q = p; q != NULL; q = q->next)
    {
        if (i >= ETH_TX_DESC_CNT)
            return ERR_IF;

Txbuffer[i].buffer = q->payload;
        Txbuffer[i].len = q->len;
        framelen += q->len;

if (i > 0)
        {
            Txbuffer[i - 1].next = &Txbuffer[i];
        }

if (q->next == NULL)
        {
            Txbuffer[i].next = NULL;
        }

i++;
    }

TxConfig.Length = framelen;
    TxConfig.TxBuffer = Txbuffer;

#ifdef ETH_TX_DUMP
    rt_kprintf("Tx dump, len= %d\r\n", framelen);
    dump_hex(&Txbuffer[0],TxConfig.Length);
#endif

if (stm32_eth_device.parent.link_status)
    {
        SCB_CleanInvalidateDCache();
        state = HAL_ETH_Transmit(&EthHandle, &TxConfig, 1000);
        if (state != HAL_OK)
        {
            LOG_W("eth transmit frame faild: %d", EthHandle.ErrorCode);
            EthHandle.ErrorCode = HAL_ETH_STATE_READY;
            EthHandle.gState = HAL_ETH_STATE_READY;
        }
    }
    else
    {
        LOG_E("eth transmit frame faild, netif not up");
    }

ret = ERR_OK;

return ret;
}

/* receive data*/
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
    uint32_t framelength = 0;
    rt_uint16_t l;
    struct pbuf *p = RT_NULL, *q;
    ETH_BufferTypeDef RxBuff;
    uint32_t alignedAddr;

if(HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK)
  {
    HAL_ETH_GetRxDataLength(&EthHandle, &framelength);

/* Build Rx descriptor to be ready for next data reception */
    HAL_ETH_BuildRxDescriptors(&EthHandle);

/* Invalidate data cache for ETH Rx Buffers */
    alignedAddr = (uint32_t)RxBuff.buffer & ~0x1F;
    SCB_InvalidateDCache_by_Addr((uint32_t *)alignedAddr, (uint32_t)RxBuff.buffer - alignedAddr + framelength);

p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
    if (p != NULL)
    {
        for (q = p, l = 0; q != NULL; q = q->next)
        {
            memcpy((rt_uint8_t *)q->payload, (rt_uint8_t *)&RxBuff.buffer[l], q->len);
            l = l + q->len;
        }
    }
  }

return p;
}

/* interrupt service routine */
void ETH_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();

HAL_ETH_IRQHandler(&EthHandle);

/* leave interrupt */
    rt_interrupt_leave();
}

void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
    rt_err_t result;
    result = eth_device_ready(&(stm32_eth_device.parent));
    if (result != RT_EOK)
        LOG_I("RxCpltCallback err = %d", result);
}

void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
    LOG_E("eth err");
}

enum {
    PHY_LINK        = (1 << 0),
    PHY_100M        = (1 << 1),
    PHY_FULL_DUPLEX = (1 << 2),
};

static void phy_linkchange()
{
    static rt_uint8_t phy_speed = 0;
    rt_uint8_t phy_speed_new = 0;
    rt_uint32_t status;

HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
    LOG_D("phy basic status reg is 0x%X", status);

if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
    {
        rt_uint32_t SR = 0;

phy_speed_new |= PHY_LINK;

HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_Status_REG, (uint32_t *)&SR);
        LOG_D("phy control status reg is 0x%X", SR);

if (PHY_Status_SPEED_100M(SR))
        {
            phy_speed_new |= PHY_100M;
        }

if (PHY_Status_FULL_DUPLEX(SR))
        {
            phy_speed_new |= PHY_FULL_DUPLEX;
        }
    }

if (phy_speed != phy_speed_new)
    {
        phy_speed = phy_speed_new;
        if (phy_speed & PHY_LINK)
        {
            LOG_D("link up");
            if (phy_speed & PHY_100M)
            {
                LOG_D("100Mbps");
                stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
            }
            else
            {
                stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
                LOG_D("10Mbps");
            }

if (phy_speed & PHY_FULL_DUPLEX)
            {
                LOG_D("full-duplex");
                stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;
            }
            else
            {
                LOG_D("half-duplex");
                stm32_eth_device.ETH_Mode = ETH_HALFDUPLEX_MODE;
            }

/* send link up. */
            eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
        }
        else
        {
            LOG_I("link down");
            eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
        }
    }
}

#ifdef PHY_USING_INTERRUPT_MODE
static void eth_phy_isr(void *args)
{
    rt_uint32_t status = 0;

HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
    LOG_D("phy interrupt status reg is 0x%X", status);

phy_linkchange();
}
#endif /* PHY_USING_INTERRUPT_MODE */

static void phy_monitor_thread_entry(void *parameter)
{
    phy_linkchange();
#ifdef PHY_USING_INTERRUPT_MODE
    /* configuration intterrupt pin */
    rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
    rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
    rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);

/* enable phy interrupt */
    HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
#if defined(PHY_INTERRUPT_CTRL_REG)
    HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
#endif
#else /* PHY_USING_INTERRUPT_MODE */
    stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
                                        NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
    if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
    {
        LOG_E("Start link change detection timer failed");
    }
#endif /* PHY_USING_INTERRUPT_MODE */
}
#define ETH_RESET_PIN "PH.2"
/* Register the EMAC device */
static int rt_hw_stm32_eth_init(void)
{
    rt_err_t state = RT_EOK;
    reset_pin = rt_pin_get(ETH_RESET_PIN);

rt_kprintf("reset pin num:%d\r\n",reset_pin);

rt_pin_mode(reset_pin, PIN_MODE_OUTPUT);
    rt_pin_write(reset_pin, PIN_HIGH);

stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
    stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;

/* OUI 00-80-E1 STMICROELECTRONICS. */
    stm32_eth_device.dev_addr[0] = 0x00;
    stm32_eth_device.dev_addr[1] = 0x80;
    stm32_eth_device.dev_addr[2] = 0xE1;
    /* generate MAC addr from 96bit unique ID (only for test). */
    stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
    stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
    stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);

stm32_eth_device.parent.parent.init      = rt_stm32_eth_init;
    stm32_eth_device.parent.parent.open      = rt_stm32_eth_open;
    stm32_eth_device.parent.parent.close     = rt_stm32_eth_close;
    stm32_eth_device.parent.parent.read      = rt_stm32_eth_read;
    stm32_eth_device.parent.parent.write     = rt_stm32_eth_write;
    stm32_eth_device.parent.parent.control   = rt_stm32_eth_control;
    stm32_eth_device.parent.parent.user_data = RT_NULL;

stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
    stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;

/* register eth device */
    state = eth_device_init(&(stm32_eth_device.parent), "e0");
    if (RT_EOK == state)
    {
        LOG_D("emac device init success");
    }
    else
    {
        LOG_E("emac device init faild: %d", state);
        state = -RT_ERROR;
    }

/* start phy monitor */
    rt_thread_t tid;
    tid = rt_thread_create("phy",
                           phy_monitor_thread_entry,
                           RT_NULL,
                           1024,
                           RT_THREAD_PRIORITY_MAX - 2,
                           2);
    if (tid != RT_NULL)
    {
        rt_thread_startup(tid);
    }
    else
    {
        state = -RT_ERROR;
    }

return state;
}
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);

#endif /* BSP_USING_ETH */
```
此处与论坛所得的代码改动主要是以下几个方面
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/4a87a70d39ec05b8bc99d429e12ea99c.png)
## 五、使用setting工具配置lwip协议栈和其他的接口的配置
1.配置总览
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/ccf9894a387de606d7f5d48d8c0cbeee.png.webp)
2.配置LWIP协议栈
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/42d2e645f996a0de1a188a593b2aff6f.png.webp)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/7e007698e53a275619cc4244409545dc.png)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/dffe5b5f697fe92b9d5f4d19ead38a7a.png)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/083d3caea0e71438f77a94b4899c30de.png)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/9a03d97f3357a41b55a523e1a35538a2.png)

3.配置board.h函数
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/2ca8558327d62fb257d03c494eb515c9.png)

4.配置hal_conf文件
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/1fcb034be13fbf0ef3b2accafcf5320a.png)

5.加入Icache和Dcache使能的代码
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/8dc733a9041e5e489c3e01942c7a1936.png.webp)

```c
static void CPU_CACHE_Enable(void)
{
  /* 使能 I-Cache */
  SCB_EnableICache();
  /* 使能 D-Cache */
  SCB_EnableDCache();

}
```
## 六、修改drv_gpio.c，增加stm32_pin_get函数
因为drv_eth驱动里面用到了自动获取复位引脚pin的引脚数的函数，但是rtthread v4.1.1生成的代码没有这个函数，导致
获取失败，因此需要增加此部分代码

```c
#define PIN_NUM(port, no) (((((port)&0xFu) << 4) | ((no)&0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin)&0xFu))

/* e.g. PE.7 */
static rt_base_t stm32_pin_get(const char *name)
{
    rt_base_t pin = 0;
    int hw_port_num, hw_pin_num = 0;
    int i, name_len;

name_len = rt_strlen(name);

if ((name_len < 4) || (name_len >= 6))
    {
        goto out;
    }
    if ((name[0] != 'P') || (name[2] != '.'))
    {
        goto out;
    }

if ((name[1] >= 'A') && (name[1] <= 'Z'))
    {
        hw_port_num = (int)(name[1] - 'A');
    }
    else
    {
        goto out;
    }

for (i = 3; i < name_len; i++)
    {
        hw_pin_num *= 10;
        hw_pin_num += name[i] - '0';
    }

pin = PIN_NUM(hw_port_num, hw_pin_num);

return pin;

out:
    rt_kprintf("Px.y  x:A~Z  y:0-15, e.g. PA.0\n");
    return -RT_EINVAL;
}
```
加到ops结构体里面去
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/bc845da9f0e337c6c21ff5ea422bd75a.png)
这里会用到

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/1a3620e03fa41a893a9259f31545bd45.png.webp)
记得根据自己网卡芯片的复位引脚改动

## 七、修改链接文件

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/fb74906035028ddb63aceb240e2e9115.png)

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240807/89f30abf55e147cc7cedd67046a25d52.png.webp)

```c
/*
 * linker script for STM32H743IITx with GNU ld
 */

/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN =0x08000000,LENGTH =2048k
RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
RxDecripSection(rw) : ORIGIN =0x30040000,LENGTH =32k
TxDecripSection(rw) : ORIGIN =0x30040060,LENGTH =32k
RxArraySection(rw) : ORIGIN =0x30040200,LENGTH =32k
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;

SECTIONS
{
    .text :
    {
        . = ALIGN(4);
        _stext = .;
        KEEP(*(.isr_vector))            /* Startup code */

. = ALIGN(4);
        *(.text)                        /* remaining code */
        *(.text.*)                      /* remaining code */
        *(.rodata)                      /* read-only data (constants) */
        *(.rodata*)
        *(.glue_7)
        *(.glue_7t)
        *(.gnu.linkonce.t*)

/* section information for finsh shell */
        . = ALIGN(4);
        __fsymtab_start = .;
        KEEP(*(FSymTab))
        __fsymtab_end = .;

. = ALIGN(4);
        __vsymtab_start = .;
        KEEP(*(VSymTab))
        __vsymtab_end = .;

/* section information for utest */
        . = ALIGN(4);
        __rt_utest_tc_tab_start = .;
        KEEP(*(UtestTcTab))
        __rt_utest_tc_tab_end = .;

/* section information for at server */
        . = ALIGN(4);
        __rtatcmdtab_start = .;
        KEEP(*(RtAtCmdTab))
        __rtatcmdtab_end = .;
        . = ALIGN(4);

/* section information for initial. */
        . = ALIGN(4);
        __rt_init_start = .;
        KEEP(*(SORT(.rti_fn*)))
        __rt_init_end = .;

. = ALIGN(4);

PROVIDE(__ctors_start__ = .);
        KEEP (*(SORT(.init_array.*)))
        KEEP (*(.init_array))
        PROVIDE(__ctors_end__ = .);

. = ALIGN(4);

_etext = .;
    } > ROM = 0

/* .ARM.exidx is sorted, so has to go in its own output section.  */
    __exidx_start = .;
    .ARM.exidx :
    {
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

/* This is used by the startup in order to initialize the .data secion */
        _sidata = .;
    } > ROM
    __exidx_end = .;
    
    .RxDecripSection (NOLOAD) : ALIGN(4)
    {
        . = ALIGN(4);
        *(.RxDecripSection)
        *(.RxDecripSection.*)
        . = ALIGN(4);
        RxDecripSection_free = .;
    } > RxDecripSection

.TxDecripSection (NOLOAD) : ALIGN(4)
    {
        . = ALIGN(4);
        *(.TxDecripSection)
        *(.TxDecripSection.*)
        . = ALIGN(4);
        TxDecripSection_free = .;
    } > TxDecripSection

.RxArraySection (NOLOAD) : ALIGN(4)
    {
        . = ALIGN(4);
        *(.RxArraySection)
        *(.RxArraySection.*)
        . = ALIGN(4);
        RxArraySection_free = .;
    } > RxArraySection

_end = .;

/* .data section which is used for initialized data */

.data : AT (_sidata)
    {
        . = ALIGN(4);
        /* This is used by the startup in order to initialize the .data secion */
        _sdata = . ;

*(.data)
        *(.data.*)
        *(.gnu.linkonce.d*)

PROVIDE(__dtors_start__ = .);
        KEEP(*(SORT(.dtors.*)))
        KEEP(*(.dtors))
        PROVIDE(__dtors_end__ = .);

. = ALIGN(4);
        /* This is used by the startup in order to initialize the .data secion */
        _edata = . ;
    } >RAM

.stack : 
    {
        . = ALIGN(4);
        _sstack = .;
        . = . + _system_stack_size;
        . = ALIGN(4);
        _estack = .;
    } >RAM

__bss_start = .;
    .bss :
    {
        . = ALIGN(4);
        /* This is used by the startup in order to initialize the .bss secion */
        _sbss = .;

*(.bss)
        *(.bss.*)
        *(COMMON)

. = ALIGN(4);
        /* This is used by the startup in order to initialize the .bss secion */
        _ebss = . ;
        
        *(.bss.init)
    } > RAM
    __bss_end = .;

_end = .;

/* Stabs debugging sections.  */
    .stab          0 : { *(.stab) }
    .stabstr       0 : { *(.stabstr) }
    .stab.excl     0 : { *(.stab.excl) }
    .stab.exclstr  0 : { *(.stab.exclstr) }
    .stab.index    0 : { *(.stab.index) }
    .stab.indexstr 0 : { *(.stab.indexstr) }
    .comment       0 : { *(.comment) }
    /* DWARF debug sections.
     * Symbols in the DWARF debugging sections are relative to the beginning
     * of the section so we begin them at 0.  */
    /* DWARF 1 */
    .debug          0 : { *(.debug) }
    .line           0 : { *(.line) }
    /* GNU DWARF 1 extensions */
    .debug_srcinfo  0 : { *(.debug_srcinfo) }
    .debug_sfnames  0 : { *(.debug_sfnames) }
    /* DWARF 1.1 and DWARF 2 */
    .debug_aranges  0 : { *(.debug_aranges) }
    .debug_pubnames 0 : { *(.debug_pubnames) }
    /* DWARF 2 */
    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
    .debug_abbrev   0 : { *(.debug_abbrev) }
    .debug_line     0 : { *(.debug_line) }
    .debug_frame    0 : { *(.debug_frame) }
    .debug_str      0 : { *(.debug_str) }
    .debug_loc      0 : { *(.debug_loc) }
    .debug_macinfo  0 : { *(.debug_macinfo) }
    /* SGI/MIPS DWARF 2 extensions */
    .debug_weaknames 0 : { *(.debug_weaknames) }
    .debug_funcnames 0 : { *(.debug_funcnames) }
    .debug_typenames 0 : { *(.debug_typenames) }
    .debug_varnames  0 : { *(.debug_varnames) }
}

```
## 附件及参考资料
rtthread工程代码
[YS_H743_PRO_CHIP(T0806).rar](https://club.rt-thread.org/file_download/5416901c0d8b99b9)

裸机测试代码
网络通信例程.rar
链接：https://pan.baidu.com/s/1Ij_yWOq3PpM8LtGpHJEHtA?pwd=nww7 
提取码：nww7

参考链接
1.https://www.eeworld.com.cn/mcu/eic667824.html
2.https://club.rt-thread.org/ask/question/4232b17f3bffe8eb.html