RT-Thread-FRDM-MCXN947上的TFT实践RT-Thread问答社区

FRDM-MCXN947上的TFT实践

发布于 2024-04-14 00:58:32 浏览：466 订阅该版

[tocm]

# 1、前言说明
本章通过FRDM-MCXN947开发板与正点原子的TFTLCD进行实践

## 1.2模块介绍
- **硬件：**
- FRDM-MCXN947开发板：

- 该开发板具有丰富的接口详细可参考[NXP官方网站](https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-n94-n54-mcus:FRDM-MCXN947 "NXP官方网站")，从下图板载资源中可看出TFTLCD可以通过flexIO进行驱动。

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/67019fb82dfd3481e5c7b7264a0681a0.png)
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240413/bc023a625fcd17727c1c238395835877.png.webp )
- FTLCD为正点原子并口屏：

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/1ade7f67d9cf90a615fd8a02a37e3ae3.png.webp)
- **软件：**
下拉rtthread代码
```shell
git clone https://github.com/RT-Thread/rt-thread.git rt-thread
```
## 1.3 软件开发
**编译配置工具：**env  从 RT-Thread 官网下载 [Env工具](https://www.rt-thread.org/download.html "Env工具")
**代码编辑器：**vscode
**下载器：**使用LinkServer.exe命令下载，来自于下载Linkserver 1.4.85 installer for Windows （nxp官网）

本人在vscode中编辑代码，通过env工具来配置和编译，在windows的PowerShell中使用LinkServer.exe命令来进行烧录。命令如下：
```shell
LinkServer.exe flash MCXN947:FRDM-MCXN947 load ./rtthread.elf
```

![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240413/85ae3b8de73fb03ebcccf99c0761bb19.png.webp)
有简单方式可以在vscode中配置tasks.json,在vscode中实现编辑、编译和烧录一站式操作，参见大佬文章：[使用VSCode 搭建 RT-Thread 关于 NXP mcxn947 开发环境（二）](https://club.rt-thread.org/ask/article/e46d421071211221.html "使用VSCode 搭建 RT-Thread 关于 NXP mcxn947 开发环境（二）")，本人比较懒，从里面搬了烧录命令来使用了。

### ***为啥不使用keil进行开发？***
主要原因是开发板一到手，下载的最新版并安装了MCXN947_DFP的keil就链接不上板子，CMSIS-DAP链接过程中会报错如下：
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/e15325826ef83b0591ac3edddaf86628.png)
我首先思考的是电脑驱动不对，去官网下载了MCU-LINK_installer_3.133，在安装过程会自动安装电脑的驱动(当然事后发现，这个电脑驱动过程其实不需要，会自动装)，仍然不起作用！在MCU-LINK_installer_3.133目录下两个脚本，可更新板载下载器固件为JLINK方式，需要配合板子上J21跳线帽来操作。
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240413/814ec4cbc70efab3b0a8e5a2b4626b37.png)
操作步骤：1.安装跳线帽；2.断电重启；3.运行program_JLINK.cmd程序进行固件更新；4更新完成后，需要取掉跳线帽，然后进行断电重启，（板子上复位按钮不行，必须断电操作）。可以看到keil识别到JLINK：
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/0d0c70cfe50598483c6c21629d55a8e9.png.webp)

**烧录过程中任然会有报错：**
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/50d4d78b3c125d87ab15f0796343b1f0.png.webp)
经过一番折腾之后，我将板载下载器固件更新回了CMSIS-DAP方式，采用了上述开发方法。

# 2、步骤说明
## 2.1 添加LCD驱动与代码修改
在ports目录下添加了LCD驱动和SConscript文件
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240413/8b25532961abd17209ee2eee1ae9ae96.png)
添加完文件后，发现LCD驱动任然没有被编译，主要原因是ports上一级目录中的SConscript文件，没有采用遍历所有目录下的SConscript文件的写法
方法一：添加遍历SConscript的写法
```python
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
    path = os.path.join(cwd, d)
    if os.path.isfile(os.path.join(path, 'SConscript')):
        objs = objs + SConscript(os.path.join(d, 'SConscript'))
```
方法二：参考其他BSP有在根SConscript文件中，单独读取board/ports/SConscript文件
```python
objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
```
在pin_mux.c中缺少对flexIO并口的配置，添加并口，CS,RS,RD,WR,ReSet引脚的配置，代码如下：

```c
/* Configure port mux of FlexIO data pins */
void FLEXIO_8080_Config_Data_Pin(void)
{
    FLEXIO_DATA0_PORT->PCR[FLEXIO_DATA0_PIN] = PORT_PCR_MUX(FLEXIO_DATA0_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D0 */
    FLEXIO_DATA1_PORT->PCR[FLEXIO_DATA1_PIN] = PORT_PCR_MUX(FLEXIO_DATA1_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D1 */
    FLEXIO_DATA2_PORT->PCR[FLEXIO_DATA2_PIN] = PORT_PCR_MUX(FLEXIO_DATA2_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D2 */
    FLEXIO_DATA3_PORT->PCR[FLEXIO_DATA3_PIN] = PORT_PCR_MUX(FLEXIO_DATA3_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D3 */
    FLEXIO_DATA4_PORT->PCR[FLEXIO_DATA4_PIN] = PORT_PCR_MUX(FLEXIO_DATA4_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D4 */
    FLEXIO_DATA5_PORT->PCR[FLEXIO_DATA5_PIN] = PORT_PCR_MUX(FLEXIO_DATA5_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D5 */
    FLEXIO_DATA6_PORT->PCR[FLEXIO_DATA6_PIN] = PORT_PCR_MUX(FLEXIO_DATA6_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D6 */
    FLEXIO_DATA7_PORT->PCR[FLEXIO_DATA7_PIN] = PORT_PCR_MUX(FLEXIO_DATA7_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D7 */

FLEXIO_DATA8_PORT->PCR[FLEXIO_DATA8_PIN] = PORT_PCR_MUX(FLEXIO_DATA8_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D8 */
    FLEXIO_DATA9_PORT->PCR[FLEXIO_DATA9_PIN] = PORT_PCR_MUX(FLEXIO_DATA9_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);       /* FXIO0_D9 */
    FLEXIO_DATA10_PORT->PCR[FLEXIO_DATA10_PIN] = PORT_PCR_MUX(FLEXIO_DATA10_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D10 */
    FLEXIO_DATA11_PORT->PCR[FLEXIO_DATA11_PIN] = PORT_PCR_MUX(FLEXIO_DATA11_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D11 */
    FLEXIO_DATA12_PORT->PCR[FLEXIO_DATA12_PIN] = PORT_PCR_MUX(FLEXIO_DATA12_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D12 */
    FLEXIO_DATA13_PORT->PCR[FLEXIO_DATA13_PIN] = PORT_PCR_MUX(FLEXIO_DATA13_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D13 */
    FLEXIO_DATA14_PORT->PCR[FLEXIO_DATA14_PIN] = PORT_PCR_MUX(FLEXIO_DATA14_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D14 */
    FLEXIO_DATA15_PORT->PCR[FLEXIO_DATA15_PIN] = PORT_PCR_MUX(FLEXIO_DATA15_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);    /* FXIO0_D15 */
}

/* Configure FLEXIO_WR pin as FlexIO function */
void FLEXIO_8080_Config_WR_FlexIO(void)
{
    FLEXIO_WR_PORT->PCR[FLEXIO_WR_PIN] = PORT_PCR_MUX(FLEXIO_WR_PIN_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
//    FLEXIO_WR_PORT->PCR[FLEXIO_WR_PIN] = PORT_PCR_MUX(FLEXIO_WR_PIN_MUX);
}
/* Configure FLEXIO_WR pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_WR_GPIO(void)
{
    FLEXIO_WR_GPIO->PSOR |= 1U << FLEXIO_WR_PIN;
    FLEXIO_WR_GPIO->PDDR |= 1U << FLEXIO_WR_PIN;
    FLEXIO_WR_PORT->PCR[FLEXIO_WR_PIN] = PORT_PCR_MUX(0) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}
void FLEXIO_8080_Set_WR_Pin(bool level)
{
    if(level)
    {
        FLEXIO_WR_GPIO->PSOR |= 1U << FLEXIO_WR_PIN;
    }
    else
    {
        FLEXIO_WR_GPIO->PCOR |= 1U << FLEXIO_WR_PIN;
    }
}

/* Configure FLEXIO_RD pin as FlexIO function */
void FLEXIO_8080_Config_RD_FlexIO(void)
{
    FLEXIO_RD_PORT->PCR[FLEXIO_RD_PIN] = PORT_PCR_MUX(FLEXIO_RD_PIN_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}

/* Configure FLEXIO_RD pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_RD_GPIO(void)
{
    FLEXIO_RD_GPIO->PSOR |= 1U << FLEXIO_RD_PIN;
    FLEXIO_RD_GPIO->PDDR |= 1U << FLEXIO_RD_PIN;
    FLEXIO_RD_PORT->PCR[FLEXIO_RD_PIN] = PORT_PCR_MUX(0) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}
/* Set FLEXIO_CS pin's level */
void FLEXIO_8080_Set_RD_Pin(bool level)
{
    if(level)
    {
        FLEXIO_RD_GPIO->PSOR |= 1U << FLEXIO_RD_PIN;
    }
    else
    {
        FLEXIO_RD_GPIO->PCOR |= 1U << FLEXIO_RD_PIN;
    }
}

/* Configure FLEXIO_CS pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_CS_GPIO(void)
{
    FLEXIO_CS_GPIO->PSOR |= 1U << FLEXIO_CS_PIN;
    FLEXIO_CS_GPIO->PDDR |= 1U << FLEXIO_CS_PIN;
    FLEXIO_CS_PORT->PCR[FLEXIO_CS_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}

/* Set FLEXIO_CS pin's level */
void FLEXIO_8080_Set_CS_Pin(bool level)
{
    if(level)
    {
        FLEXIO_CS_GPIO->PSOR |= 1U << FLEXIO_CS_PIN;
    }
    else
    {
        FLEXIO_CS_GPIO->PCOR |= 1U << FLEXIO_CS_PIN;
    }
}

/* Configure RS pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_RS_GPIO(void)
{
    FLEXIO_RS_GPIO->PSOR |= 1U << FLEXIO_RS_PIN;
    FLEXIO_RS_GPIO->PDDR |= 1U << FLEXIO_RS_PIN;
    FLEXIO_RS_PORT->PCR[FLEXIO_RS_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}

/* Set RS pin's level */
void FLEXIO_8080_Set_RS_Pin(bool level)
{
    if(level)
    {
        FLEXIO_RS_GPIO->PSOR |= 1U << FLEXIO_RS_PIN;
    }
    else
    {
        FLEXIO_RS_GPIO->PCOR |= 1U << FLEXIO_RS_PIN;
    }
}

/* Configure ReSet pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_ReSet_GPIO(void)
{
    FLEXIO_ReSet_GPIO->PSOR |= 1U << FLEXIO_ReSet_PIN;
    FLEXIO_ReSet_GPIO->PDDR |= 1U << FLEXIO_ReSet_PIN;
    FLEXIO_ReSet_PORT->PCR[FLEXIO_ReSet_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}

/* Set ReSet pin's level */
void FLEXIO_8080_Set_ReSet_Pin(bool level)
{
    if(level)
    {
        FLEXIO_ReSet_GPIO->PSOR |= 1U << FLEXIO_ReSet_PIN;
    }
    else
    {
        FLEXIO_ReSet_GPIO->PCOR |= 1U << FLEXIO_ReSet_PIN;
    }
}

/* Configure ReSet pin as GPIO function and outputting high level */
void FLEXIO_8080_Config_Te_GPIO(void)
{
    FLEXIO_Te_GPIO->PSOR |= 1U << FLEXIO_Te_PIN;
    FLEXIO_Te_GPIO->PDDR |= 1U << FLEXIO_Te_PIN;
    FLEXIO_Te_PORT->PCR[FLEXIO_Te_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
}

/* Set ReSet pin's level */
void FLEXIO_8080_Set_Te_Pin(bool level)
{
    if(level)
    {
        FLEXIO_Te_GPIO->PSOR |= 1U << FLEXIO_Te_PIN;
    }
    else
    {
        FLEXIO_Te_GPIO->PCOR |= 1U << FLEXIO_Te_PIN;
    }
}

```
## 2.2 编译运行程序
[LCDTFT程序运行.mp4](https://club.rt-thread.org/file_download/15c229bf648c2991)
![0b5018b41c7deda43f75 -big-portrait.gif](https://oss-club.rt-thread.org/uploads/20240416/4b41ec9e5339414f9001231213465899.gif)
## 2.3 lvgl使用
在menuconfig中启用lvgl
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/c890da27b81c3facf1f4b8f3e84238ae.png)
在applicaions中添加了lvgl相关的配置和接口文件
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/72212169e5d905bdd69c5db2f6488544.png)
在lv_conf.h中定义了一下几个宏定义
```c
#define LV_COLOR_16_SWAP    0   /*spi通信时设置1 */
#define LV_COLOR_DEPTH      16  /*颜色深度 */
#define LV_USE_PERF_MONITOR 1   /*启用帧率监控 */
```
在lv_port_disp.c中定义了显示分辨率、显示buffer、显示更新的回调函数,并在lv_port_disp_init函数里进行注册
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/af723325c813439a48cd524ae375ed6e.png)
在回调函数里调用lcd驱动里的区域填充函数
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/70152c854c0e5ea271f2e857424ae6e9.png)
# 2.4 lvgl验证
跑一个benchmark看一看效果
[sdf.mp4](https://club.rt-thread.org/file_download/86b25c6fb1cde3d9)
![sdf -big-portrait.gif](https://oss-club.rt-thread.org/uploads/20240416/707c0f628112a151ae111aea53f9d3c8.gif)
lvgl跑出来的帧率为18
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/1c73ccf75883f3e4cb9e8c7dc8a4db15.png.webp)
采用编译优化等级O1，导致LCD功能有问题，屏幕不显示。于是LCD驱动部分代码采用O0，其他代码采用O1，修改编译脚本rtconfig.py,脚本默认走的是debug分支，将其修改到release分支
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/4045101a0caffd543b973447ef2d641e.png)
当然这个修改会对整个工程产生影响，需要在LCD驱动部分编译脚本中添加局部编译参数
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/29422f07254b0562f4ca5767416b40f4.png)
lvgl帧率提升至26
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/9d666abb5ea7161e84de309602c50099.png.webp)
当然尝试了双buf和优化等级O3，帧率没有再提高
# 3 测试代码
[frdm-mcxn947.7z](https://club.rt-thread.org/file_download/abeb4979abe82a68)
# 总结
第一次使用NXP的芯片，TFT模块功能成功使用起来，但是keil的开发环境不太熟悉，上述过程中仍有两在keil使用中有下载器使用的两个遗留问题，欢迎大佬解答。
一是使用CMSIS-DAP下载报错：
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240416/e15325826ef83b0591ac3edddaf86628.png)
二是使用JLINK下载报错：
![screenshot_image.png](https://oss-club.rt-thread.org/uploads/20240414/50d4d78b3c125d87ab15f0796343b1f0.png.webp)