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AUDIO
sai音频接口
WM8978
使用bsp下的stm32f429-atk-apollo里面的wm8978驱动以及wavplay软件包没有声音
发布于 2024-05-22 19:49:26 浏览：174
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1、drv_sound.c文件如下 ```c /* * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-07-28 Ernest the first version */ #include "board.h" #include "drv_wm8978.h" #include "drv_sound.h" #define DBG_TAG "drv.sound" #define DBG_LVL DBG_INFO #include <rtdbg.h> #define CODEC_I2C_NAME ("i2c1") #define TX_DMA_FIFO_SIZE (2048) struct drv_sai _sai_a = {0}; struct stm32_audio { struct rt_i2c_bus_device *i2c_bus; struct rt_audio_device audio; struct rt_audio_configure replay_config; int replay_volume; rt_uint8_t *tx_fifo; rt_bool_t startup; }; struct stm32_audio _stm32_audio_play = {0}; /* sample_rate, PLLI2SN(50.7), PLLI2SQ, PLLI2SDivQ, MCKDIV */ const rt_uint32_t SAI_PSC_TBL[][5] = { {AUDIO_FREQUENCY_048K, 206, 7, 0, 12}, {AUDIO_FREQUENCY_044K, 257, 2, 18, 2}, {AUDIO_FREQUENCY_032K, 206, 7, 0, 6}, {AUDIO_FREQUENCY_022K, 257, 2, 18, 1}, {AUDIO_FREQUENCY_016K, 206, 7, 0, 3}, {AUDIO_FREQUENCY_011K, 257, 2, 18, 0}, {AUDIO_FREQUENCY_008K, 206, 7, 0, 2}, }; void SAIA_samplerate_set(rt_uint32_t freq) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; int i; /* check frequence */ for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++) { if ((freq) == SAI_PSC_TBL[i][0])break; } if (i == (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0]))) { LOG_E("Can not support this frequence: %d.", freq); return; } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1]; PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2]; PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); __HAL_SAI_DISABLE(&_sai_a.hsai); _sai_a.hsai.Init.AudioFrequency = freq; HAL_SAI_Init(&_sai_a.hsai); __HAL_SAI_ENABLE(&_sai_a.hsai); } void SAIA_channels_set(rt_uint16_t channels) { if (channels == 2) { _sai_a.hsai.Init.MonoStereoMode = SAI_STEREOMODE; } else { _sai_a.hsai.Init.MonoStereoMode = SAI_MONOMODE; } __HAL_SAI_DISABLE(&_sai_a.hsai); HAL_SAI_Init(&_sai_a.hsai); __HAL_SAI_ENABLE(&_sai_a.hsai); } void SAIA_samplebits_set(rt_uint16_t samplebits) { switch (samplebits) { case 16: _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; break; case 24: _sai_a.hsai.Init.DataSize = SAI_DATASIZE_24; break; case 32: _sai_a.hsai.Init.DataSize = SAI_DATASIZE_32; break; default: _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; break; } __HAL_SAI_DISABLE(&_sai_a.hsai); HAL_SAI_Init(&_sai_a.hsai); __HAL_SAI_ENABLE(&_sai_a.hsai); } void SAIA_config_set(struct rt_audio_configure config) { SAIA_channels_set(config.channels); SAIA_samplerate_set(config.samplerate); SAIA_samplebits_set(config.samplebits); } /* initial sai A */ rt_err_t SAIA_config_init(void) { _sai_a.hsai.Instance = SAI1_Block_A; _sai_a.hsai.Init.AudioMode = SAI_MODEMASTER_TX; _sai_a.hsai.Init.Synchro = SAI_ASYNCHRONOUS; _sai_a.hsai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; _sai_a.hsai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; _sai_a.hsai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; _sai_a.hsai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; _sai_a.hsai.Init.Protocol = SAI_FREE_PROTOCOL; _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; _sai_a.hsai.Init.FirstBit = SAI_FIRSTBIT_MSB; _sai_a.hsai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; //frame _sai_a.hsai.FrameInit.FrameLength = 64; _sai_a.hsai.FrameInit.ActiveFrameLength = 32; _sai_a.hsai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; _sai_a.hsai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; _sai_a.hsai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; //slot _sai_a.hsai.SlotInit.FirstBitOffset = 0; _sai_a.hsai.SlotInit.SlotSize = SAI_SLOTSIZE_32B; _sai_a.hsai.SlotInit.SlotNumber = 2; _sai_a.hsai.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; HAL_SAI_Init(&_sai_a.hsai); __HAL_SAI_ENABLE(&_sai_a.hsai); return RT_EOK; } rt_err_t SAIA_tx_dma(void) { __HAL_RCC_DMA2_CLK_ENABLE(); __HAL_LINKDMA(&_sai_a.hsai, hdmatx, _sai_a.hdma); _sai_a.hdma.Instance = DMA2_Stream3; _sai_a.hdma.Init.Channel = DMA_CHANNEL_0; _sai_a.hdma.Init.Direction = DMA_MEMORY_TO_PERIPH; _sai_a.hdma.Init.PeriphInc = DMA_PINC_DISABLE; _sai_a.hdma.Init.MemInc = DMA_MINC_ENABLE; _sai_a.hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; _sai_a.hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; _sai_a.hdma.Init.Mode = DMA_CIRCULAR; _sai_a.hdma.Init.Priority = DMA_PRIORITY_HIGH; _sai_a.hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE; _sai_a.hdma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; _sai_a.hdma.Init.MemBurst = DMA_MBURST_SINGLE; _sai_a.hdma.Init.PeriphBurst = DMA_PBURST_SINGLE; HAL_DMA_DeInit(&_sai_a.hdma); HAL_DMA_Init(&_sai_a.hdma); __HAL_DMA_DISABLE(&_sai_a.hdma); __HAL_DMA_ENABLE_IT(&_sai_a.hdma, DMA_IT_TC); __HAL_DMA_CLEAR_FLAG(&_sai_a.hdma, DMA_FLAG_TCIF3_7); /* set nvic */ HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); return RT_EOK; } void DMA2_Stream3_IRQHandler(void) { rt_interrupt_enter(); HAL_DMA_IRQHandler(_sai_a.hsai.hdmatx); rt_interrupt_leave(); } void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) { rt_audio_tx_complete(&_stm32_audio_play.audio); } void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) { rt_audio_tx_complete(&_stm32_audio_play.audio); } rt_err_t sai_a_init() { /* set sai_a DMA */ SAIA_tx_dma(); SAIA_config_init(); return RT_EOK; } static rt_err_t stm32_player_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) { rt_err_t result = RT_EOK; struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data; LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); switch (caps->main_type) { case AUDIO_TYPE_QUERY: /* query the types of hw_codec device */ { switch (caps->sub_type) { case AUDIO_TYPE_QUERY: caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; break; default: result = -RT_ERROR; break; } break; } case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ { switch (caps->sub_type) { case AUDIO_DSP_PARAM: caps->udata.config.channels = st_audio->replay_config.channels; caps->udata.config.samplebits = st_audio->replay_config.samplebits; caps->udata.config.samplerate = st_audio->replay_config.samplerate; break; case AUDIO_DSP_SAMPLERATE: caps->udata.config.samplerate = st_audio->replay_config.samplerate; break; case AUDIO_DSP_CHANNELS: caps->udata.config.channels = st_audio->replay_config.channels; break; case AUDIO_DSP_SAMPLEBITS: caps->udata.config.samplebits = st_audio->replay_config.samplebits; break; default: result = -RT_ERROR; break; } break; } case AUDIO_TYPE_MIXER: /* report the Mixer Units */ { switch (caps->sub_type) { case AUDIO_MIXER_QUERY: caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_LINE; break; case AUDIO_MIXER_VOLUME: caps->udata.value = st_audio->replay_volume; break; case AUDIO_MIXER_LINE: break; default: result = -RT_ERROR; break; } break; } default: result = -RT_ERROR; break; } return result; } static rt_err_t stm32_player_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) { rt_err_t result = RT_EOK; struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data; LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); switch (caps->main_type) { case AUDIO_TYPE_MIXER: { switch (caps->sub_type) { case AUDIO_MIXER_MUTE: { /* set mute mode */ wm8978_mute_enabled(_stm32_audio_play.i2c_bus, RT_FALSE); break; } case AUDIO_MIXER_VOLUME: { int volume = caps->udata.value; st_audio->replay_volume = volume; /* set mixer volume */ wm8978_set_volume(_stm32_audio_play.i2c_bus, volume); break; } default: result = -RT_ERROR; break; } break; } case AUDIO_TYPE_OUTPUT: { switch (caps->sub_type) { case AUDIO_DSP_PARAM: { struct rt_audio_configure config = caps->udata.config; st_audio->replay_config.samplerate = config.samplerate; st_audio->replay_config.samplebits = config.samplebits; st_audio->replay_config.channels = config.channels; SAIA_config_set(config); break; } case AUDIO_DSP_SAMPLERATE: { st_audio->replay_config.samplerate = caps->udata.config.samplerate; SAIA_samplerate_set(caps->udata.config.samplerate); break; } case AUDIO_DSP_CHANNELS: { st_audio->replay_config.channels = caps->udata.config.channels; SAIA_channels_set(caps->udata.config.channels); break; } case AUDIO_DSP_SAMPLEBITS: { st_audio->replay_config.samplebits = caps->udata.config.samplebits; SAIA_samplebits_set(caps->udata.config.samplebits); break; } default: result = -RT_ERROR; break; } break; } default: break; } return result; } static rt_err_t stm32_player_init(struct rt_audio_device *audio) { /* initialize wm8978 */ _stm32_audio_play.i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME); sai_a_init(); wm8978_init(_stm32_audio_play.i2c_bus); return RT_EOK; } static rt_err_t stm32_player_start(struct rt_audio_device *audio, int stream) { if (stream == AUDIO_STREAM_REPLAY) { HAL_SAI_Transmit_DMA(&_sai_a.hsai, _stm32_audio_play.tx_fifo, TX_DMA_FIFO_SIZE / 2); wm8978_player_start(_stm32_audio_play.i2c_bus); } return RT_EOK; } static rt_err_t stm32_player_stop(struct rt_audio_device *audio, int stream) { if (stream == AUDIO_STREAM_REPLAY) { HAL_SAI_DMAStop(&_sai_a.hsai); } return RT_EOK; } static void stm32_player_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) { /** * TX_FIFO * +----------------+----------------+ * | block1 | block2 | * +----------------+----------------+ * \ block_size / */ info->buffer = _stm32_audio_play.tx_fifo; info->total_size = TX_DMA_FIFO_SIZE; info->block_size = TX_DMA_FIFO_SIZE / 2; info->block_count = 2; } static struct rt_audio_ops _p_audio_ops = { .getcaps = stm32_player_getcaps, .configure = stm32_player_configure, .init = stm32_player_init, .start = stm32_player_start, .stop = stm32_player_stop, .transmit = RT_NULL, .buffer_info = stm32_player_buffer_info, }; int rt_hw_sound_init(void) { rt_uint8_t *tx_fifo; /* player */ tx_fifo = rt_malloc(TX_DMA_FIFO_SIZE); if (tx_fifo == RT_NULL) { return -RT_ENOMEM; } rt_memset(tx_fifo, 0, TX_DMA_FIFO_SIZE); _stm32_audio_play.tx_fifo = tx_fifo; /* register sound device */ _stm32_audio_play.audio.ops = &_p_audio_ops; rt_audio_register(&_stm32_audio_play.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &_stm32_audio_play); return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_sound_init); ``` 2、drv_wm8978.c文件如下 ```c /* * Copyright (c) 2006-2018, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-14 ZeroFree first implementation * 2019-07-28 Ernest perfect player, add record funciton and other APIs */ #include <rtthread.h> #include <rtdevice.h> #include "drv_wm8978.h" #include <stdlib.h> /* Register Definitions */ #define REG_SOFTWARE_RESET ((uint16_t)0) #define REG_POWER_MANAGEMENT1 ((uint16_t)(1 << 9)) #define REG_POWER_MANAGEMENT2 ((uint16_t)(2 << 9)) #define REG_POWER_MANAGEMENT3 ((uint16_t)(3 << 9)) #define REG_AUDIO_INTERFACE ((uint16_t)(4 << 9)) #define REG_COMPANDING ((uint16_t)(5 << 9)) #define REG_CLOCK_GEN ((uint16_t)(6 << 9)) #define REG_ADDITIONAL ((uint16_t)(7 << 9)) #define REG_GPIO ((uint16_t)(8 << 9)) #define REG_JACK_DETECT1 ((uint16_t)(9 << 9)) #define REG_DAC ((uint16_t)(10 << 9)) #define REG_LEFT_DAC_VOL ((uint16_t)(11 << 9)) #define REG_RIGHT_DAC_VOL ((uint16_t)(12 << 9)) #define REG_JACK_DETECT2 ((uint16_t)(13 << 9)) #define REG_ADC ((uint16_t)(14 << 9)) #define REG_LEFT_ADC_VOL ((uint16_t)(15 << 9)) #define REG_RIGHT_ADC_VOL ((uint16_t)(16 << 9)) #define REG_EQ1 ((uint16_t)(18 << 9)) #define REG_EQ2 ((uint16_t)(19 << 9)) #define REG_EQ3 ((uint16_t)(20 << 9)) #define REG_EQ4 ((uint16_t)(21 << 9)) #define REG_EQ5 ((uint16_t)(22 << 9)) #define REG_DAC_LIMITER1 ((uint16_t)(24 << 9)) #define REG_DAC_LIMITER2 ((uint16_t)(25 << 9)) #define REG_NOTCH_FILTER1 ((uint16_t)(27 << 9)) #define REG_NOTCH_FILTER2 ((uint16_t)(28 << 9)) #define REG_NOTCH_FILTER3 ((uint16_t)(29 << 9)) #define REG_NOTCH_FILTER4 ((uint16_t)(30 << 9)) #define REG_ALC1 ((uint16_t)(32 << 9)) #define REG_ALC2 ((uint16_t)(33 << 9)) #define REG_ALC3 ((uint16_t)(34 << 9)) #define REG_NOISE_GATE ((uint16_t)(35 << 9)) #define REG_PLL_N ((uint16_t)(36 << 9)) #define REG_PLL_K1 ((uint16_t)(37 << 9)) #define REG_PLL_K2 ((uint16_t)(38 << 9)) #define REG_PLL_K3 ((uint16_t)(39 << 9)) #define REG_3D ((uint16_t)(41 << 9)) #define REG_BEEP ((uint16_t)(43 << 9)) #define REG_INPUT ((uint16_t)(44 << 9)) #define REG_LEFT_PGA_GAIN ((uint16_t)(45 << 9)) #define REG_RIGHT_PGA_GAIN ((uint16_t)(46 << 9)) #define REG_LEFT_ADC_BOOST ((uint16_t)(47 << 9)) #define REG_RIGHT_ADC_BOOST ((uint16_t)(48 << 9)) #define REG_OUTPUT ((uint16_t)(49 << 9)) #define REG_LEFT_MIXER ((uint16_t)(50 << 9)) #define REG_RIGHT_MIXER ((uint16_t)(51 << 9)) #define REG_LOUT1_VOL ((uint16_t)(52 << 9)) #define REG_ROUT1_VOL ((uint16_t)(53 << 9)) #define REG_LOUT2_VOL ((uint16_t)(54 << 9)) #define REG_ROUT2_VOL ((uint16_t)(55 << 9)) #define REG_OUT3_MIXER ((uint16_t)(56 << 9)) #define REG_OUT4_MIXER ((uint16_t)(57 << 9)) // R01 REG_POWER_MANAGEMENT1 #define BUFDCOPEN (1 << 8) #define OUT4MIXEN (1 << 7) #define OUT3MIXEN (1 << 6) #define PLLEN (1 << 5) #define MICBEN (1 << 4) #define BIASEN (1 << 3) #define BUFIOEN (1 << 2) #define VMIDSEL_OFF (0) #define VMIDSEL_75K (1) #define VMIDSEL_300K (2) #define VMIDSEL_5K (3) // R02 REG_POWER_MANAGEMENT2 #define ROUT1EN (1 << 8) #define LOUT1EN (1 << 7) #define SLEEP (1 << 6) #define BOOSTENR (1 << 5) #define BOOSTENL (1 << 4) #define INPPGAENR (1 << 3) #define INPPGAENL (1 << 2) #define ADCENR (1 << 1) #define ADCENL (1) // R03 REG_POWER_MANAGEMENT3 #define OUT4EN (1 << 8) #define OUT3EN (1 << 7) #define LOUT2EN (1 << 6) #define ROUT2EN (1 << 5) #define RMIXEN (1 << 3) #define LMIXEN (1 << 2) #define DACENR (1 << 1) #define DACENL (1) // R04 REG_AUDIO_INTERFACE #define BCP_NORMAL (0) #define BCP_INVERTED (1 << 8) #define LRP_NORMAL (0) #define LRP_INVERTED (1 << 7) #define WL_16BITS (0) #define WL_20BITS (1 << 5) #define WL_24BITS (2 << 5) // Default value #define WL_32BITS (3 << 5) #define FMT_RIGHT_JUSTIFIED (0) #define FMT_LEFT_JUSTIFIED (1 << 3) #define FMT_I2S (2 << 3) // Default value #define FMT_PCM (3 << 3) #define DACLRSWAP (1 << 2) #define ADCLRSWAP (1 << 1) #define MONO (1) // R05 REG_COMPANDING #define WL8 (1 << 5) #define DAC_COMP_OFF (0) // Default value #define DAC_COMP_ULAW (2 << 3) #define DAC_COMP_ALAW (3 << 3) #define ADC_COMP_OFF (0) // Default value #define ADC_COMP_ULAW (2 << 1) #define ADC_COMP_ALAW (3 << 1) #define LOOPBACK (1) // R06 REG_CLOCK_GEN #define CLKSEL_MCLK (0) #define CLKSEL_PLL (1 << 8) // Default value #define MCLK_DIV1 (0) #define MCLK_DIV1_5 (1 << 5) #define MCLK_DIV2 (2 << 5) // Default value #define MCLK_DIV3 (3 << 5) #define MCLK_DIV4 (4 << 5) #define MCLK_DIV6 (5 << 5) #define MCLK_DIV8 (6 << 5) #define MCLK_DIV12 (7 << 5) #define BCLK_DIV1 (0) // Default value #define BCLK_DIV2 (1 << 2) #define BCLK_DIV4 (2 << 2) #define BCLK_DIV8 (3 << 2) #define BCLK_DIV16 (4 << 2) #define BCLK_DIV32 (5 << 2) #define MS (1) // R07 REG_ADDITIONAL #define WM_SR_48KHZ (0) // Default value #define WM_SR_32KHZ (1 << 1) #define WM_SR_24KHZ (2 << 1) #define WM_SR_16KHZ (3 << 1) #define WM_SR_12KHZ (4 << 1) #define WM_SR_8KHZ (5 << 1) #define SLOWCLKEN (1) // R08 REG_GPIO #define OPCLK_DIV1 (0) // Default value #define OPCLK_DIV2 (1 << 4) #define OPCLK_DIV3 (2 << 4) #define OPCLK_DIV4 (3 << 4) #define GPIO1POL_NONINVERTED (0) // Default value #define GPIO1POL_INVERTED (1 << 3) #define GPIO1SEL_INPUT (0) // Default value #define GPIO1SEL_TEMP_OK (2) #define GPIO1SEL_AMUTE_ACTIVE (3) #define GPIO1SEL_PLL_CLK_OP (4) #define GPIO1SEL_PLL_LOCK (5) #define GPIO1SEL_LOGIC1 (6) #define GPIO1SEL_LOGIC0 (7) // R09 REG_JACK_DETECT1 #define JD_VMID_EN1 (1 << 8) #define JD_VMID_EN0 (1 << 7) #define JD_EN (1 << 6) #define JD_SEL_GPIO1 (0 << 4) // Default value #define JD_SEL_GPIO2 (1 << 4) #define JD_SEL_GPIO3 (2 << 4) // R10 REG_DAC #define SOFTMUTE (1 << 6) #define DACOSR128 (1 << 3) #define AMUTE (1 << 2) #define DACPOLR (1 << 1) #define DACPOLL (1) // R11 & R12 REG_LEFT_DAC_VOL & REG_RIGHT_DAC_VOL #define DACVU (1 << 8) #define DACVOL_POS (0) #define DACVOL_MASK (0xFF) // R13 REG_JACK_DETECT2 #define JD_OUT4_EN1 (1 << 7) #define JD_OUT3_EN1 (1 << 6) #define JD_OUT2_EN1 (1 << 5) #define JD_OUT1_EN1 (1 << 4) #define JD_OUT4_EN0 (1 << 3) #define JD_OUT3_EN0 (1 << 2) #define JD_OUT2_EN0 (1 << 1) #define JD_OUT1_EN0 (1) // R14 REG_ADC #define HPFEN (1 << 8) #define HPFAPP (1 << 7) #define HPFCUT_POS (4) #define HPFCUT_MASK (7) #define HPFCUT_0 (0) #define HPFCUT_1 (1 << 4) #define HPFCUT_2 (2 << 4) #define HPFCUT_3 (3 << 4) #define HPFCUT_4 (4 << 4) #define HPFCUT_5 (5 << 4) #define HPFCUT_6 (6 << 4) #define HPFCUT_7 (7 << 4) #define ADCOSR128 (1 << 3) #define ADCRPOL (1 << 1) #define ADCLPOL (1) // R15 & R16 REG_LEFT_ADC_VOL & REG_RIGHT_ADC_VOL #define ADCVU (1 << 8) #define ADCVOL_POS (0) #define ADCVOL_MASK (0xFF) // R18 REG_EQ1 #define EQ3DMODE_ADC (0) #define EQ3DMODE_DAC (1 << 8) // Default value #define EQ1C_80HZ (0) #define EQ1C_105HZ (1 << 5) // Default value #define EQ1C_135HZ (2 << 5) #define EQ1C_175HZ (3 << 5) // R19 REG_EQ2 #define EQ2BW_NARROW (0) // Default value #define EQ2BW_WIDE (1 << 8) #define EQ2C_230HZ (0) #define EQ2C_300HZ (1 << 5) // Default value #define EQ2C_385HZ (2 << 5) #define EQ2C_500HZ (3 << 5) // R20 REG_EQ3 #define EQ3BW_NARROW (0) // Default value #define EQ3BW_WIDE (1 << 8) #define EQ3C_650HZ (0) #define EQ3C_850HZ (1 << 5) // Default value #define EQ3C_1_1KHZ (2 << 5) #define EQ3C_1_4KHZ (3 << 5) // R21 REG_EQ4 #define EQ4BW_NARROW (0) // Default value #define EQ4BW_WIDE (1 << 8) #define EQ4C_1_8KHZ (0) #define EQ4C_2_4KHZ (1 << 5) // Default value #define EQ4C_3_2KHZ (2 << 5) #define EQ4C_4_1KHZ (3 << 5) // R22 REG_EQ5 #define EQ5C_5_3KHZ (0) #define EQ5C_6_9KHZ (1 << 5) // Default value #define EQ5C_9KHZ (2 << 5) #define EQ5C_11_7KHZ (3 << 5) // R18 - R22 #define EQC_POS (5) #define EQC_MASK (3) #define EQG_POS (0) #define EQG_MASK (31) // R24 REG_DAC_LIMITER1 #define LIMEN (1 << 8) #define LIMDCY_POS (4) #define LIMDCY_MASK (15) #define LIMDCY_750US (0) #define LIMDCY_1_5MS (1 << 4) #define LIMDCY_3MS (2 << 4) #define LIMDCY_6MS (3 << 4) // Default value #define LIMDCY_12MS (4 << 4) #define LIMDCY_24MS (5 << 4) #define LIMDCY_48MS (6 << 4) #define LIMDCY_96MS (7 << 4) #define LIMDCY_192MS (8 << 4) #define LIMDCY_384MS (9 << 4) #define LIMDCY_768MS (10 << 4) #define LIMATK_POS (0) #define LIMATK_MASK (15) #define LIMATK_94US (0) #define LIMATK_188US (1) #define LIMATK_375US (2) // Default value #define LIMATK_750US (3) #define LIMATK_1_5MS (4) #define LIMATK_3MS (5) #define LIMATK_6MS (6) #define LIMATK_12MS (7) #define LIMATK_24MS (8) #define LIMATK_48MS (9) #define LIMATK_96MS (10) #define LIMATK_192MS (11) // R25 REG_DAC_LIMITER2 #define LIMLVL_POS (4) #define LIMLVL_MASK (7) #define LIMLVL_N1DB (0) // Default value #define LIMLVL_N2DB (1 << 4) #define LIMLVL_N3DB (2 << 4) #define LIMLVL_N4DB (3 << 4) #define LIMLVL_N5DB (4 << 4) #define LIMLVL_N6DB (5 << 4) #define LIMBOOST_POS (0) #define LIMBOOST_MASK (15) #define LIMBOOST_0DB (0) #define LIMBOOST_1DB (1) #define LIMBOOST_2DB (2) #define LIMBOOST_3DB (3) #define LIMBOOST_4DB (4) #define LIMBOOST_5DB (5) #define LIMBOOST_6DB (6) #define LIMBOOST_7DB (7) #define LIMBOOST_8DB (8) #define LIMBOOST_9DB (9) #define LIMBOOST_10DB (10) #define LIMBOOST_11DB (11) #define LIMBOOST_12DB (12) // R27 - R30 REG_NOTCH_FILTER1 - REG_NOTCH_FILTER4 #define NFU (1 << 8) #define NFEN (1 << 7) #define NFA_POS (0) #define NFA_MASK (127) // R32 REG_ALC1 #define ALCSEL_OFF (0) // Default value #define ALCSEL_RIGHT_ONLY (1 << 7) #define ALCSEL_LEFT_ONLY (2 << 7) #define ALCSEL_BOTH_ON (3 << 7) #define ALCMAXGAIN_POS (3) #define ALCMAXGAIN_MASK (7) #define ALCMAXGAIN_N6_75DB (0) #define ALCMAXGAIN_N0_75DB (1 << 3) #define ALCMAXGAIN_5_25DB (2 << 3) #define ALCMAXGAIN_11_25DB (3 << 3) #define ALCMAXGAIN_17_25DB (4 << 3) #define ALCMAXGAIN_23_25DB (5 << 3) #define ALCMAXGAIN_29_25DB (6 << 3) #define ALCMAXGAIN_35_25DB (7 << 3) // Default value #define ALCMINGAIN_POS (0) #define ALCMINGAIN_MASK (7) #define ALCMINGAIN_N12DB (0) // Default value #define ALCMINGAIN_N6DB (1) #define ALCMINGAIN_0DB (2) #define ALCMINGAIN_6DB (3) #define ALCMINGAIN_12DB (4) #define ALCMINGAIN_18DB (5) #define ALCMINGAIN_24DB (6) #define ALCMINGAIN_30DB (7) // R33 REG_ALC2 #define ALCHLD_POS (4) #define ALCHLD_MASK (15) #define ALCHLD_0MS (0) // Default value #define ALCHLD_2_67MS (1 << 4) #define ALCHLD_5_33MS (2 << 4) #define ALCHLD_10_67MS (3 << 4) #define ALCHLD_21_33MS (4 << 4) #define ALCHLD_42_67MS (5 << 4) #define ALCHLD_85_33MS (6 << 4) #define ALCHLD_170_67MS (7 << 4) #define ALCHLD_341_33MS (8 << 4) #define ALCHLD_682_67MS (9 << 4) #define ALCHLD_1_36S (10 << 4) #define ALCLVL_POS (0) #define ALCLVL_MASK (15) #define ALCLVL_N22_5DBFS (0) #define ALCLVL_N21DBFS (1) #define ALCLVL_N19_5DBFS (2) #define ALCLVL_N18DBFS (3) #define ALCLVL_N16_5DBFS (4) #define ALCLVL_N15DBFS (5) #define ALCLVL_N13_5DBFS (6) #define ALCLVL_N12DBFS (7) #define ALCLVL_N10_5DBFS (8) #define ALCLVL_N9DBFS (9) #define ALCLVL_N7_5DBFS (10) #define ALCLVL_N6DBFS (11) // Default value #define ALCLVL_N4_5DBFS (12) #define ALCLVL_N3DBFS (13) #define ALCLVL_N1_5DBFS (14) // R34 REG_ALC3 #define ALCMODE_ALC (0) // Default value #define ALCMODE_LIMITER (1 << 8) #define ALCDCY_POS (4) #define ALCDCY_MASK (15) #define ALCDCY_0 (0) #define ALCDCY_1 (1 << 4) #define ALCDCY_2 (2 << 4) #define ALCDCY_3 (3 << 4) // Default value #define ALCDCY_4 (4 << 4) #define ALCDCY_5 (5 << 4) #define ALCDCY_6 (6 << 4) #define ALCDCY_7 (7 << 4) #define ALCDCY_8 (8 << 4) #define ALCDCY_9 (9 << 4) #define ALCDCY_10 (10 << 4) #define ALCATK_POS (0) #define ALCATK_MASK (15) #define ALCATK_0 (0) #define ALCATK_1 (1) #define ALCATK_2 (2) // Default value #define ALCATK_3 (3) #define ALCATK_4 (4) #define ALCATK_5 (5) #define ALCATK_6 (6) #define ALCATK_7 (7) #define ALCATK_8 (8) #define ALCATK_9 (9) #define ALCATK_10 (10) // R35 REG_NOISE_GATE #define NGEN (1 << 3) #define NGTH_POS (0) #define NGTH_MASK (7) #define NGTH_N39DB (0) // Default value #define NGTH_N45DB (1) #define NGTH_N51DB (2) #define NGTH_N57DB (3) #define NGTH_N63DB (4) #define NGTH_N69DB (5) #define NGTH_N75DB (6) #define NGTH_N81DB (7) // R36 REG_PLL_N #define PLLPRESCALE (1 << 4) #define PLLN_POS (0) #define PLLN_MASK (15) // R37 - R39 REG_PLL_K1 - REG_PLL_K3 #define PLLK1_POS (0) #define PLLK1_MASK (63) #define PLLK2_POS (0) #define PLLK2_MASK (511) #define PLLK3_POS (0) #define PLLK3_MASK (511) // R41 REG_3D #define DEPTH3D_POS (0) #define DEPTH3D_MASK (15) #define DEPTH3D_0 (0) // Default value #define DEPTH3D_6_67 (1) #define DEPTH3D_13_33 (2) #define DEPTH3D_20 (3) #define DEPTH3D_26_67 (4) #define DEPTH3D_33_33 (5) #define DEPTH3D_40 (6) #define DEPTH3D_46_67 (7) #define DEPTH3D_53_33 (8) #define DEPTH3D_60 (9) #define DEPTH3D_66_67 (10) #define DEPTH3D_73_33 (11) #define DEPTH3D_80 (12) #define DEPTH3D_86_67 (13) #define DEPTH3D_93_33 (14) #define DEPTH3D_100 (15) // R43 REG_BEEP #define MUTERPGA2INV (1 << 5) #define INVROUT2 (1 << 4) #define BEEPVOL_POS (1) #define BEEPVOL_MASK (7) #define BEEPVOL_N15DB (0) #define BEEPVOL_N12DB (1 << 1) #define BEEPVOL_N9DB (2 << 1) #define BEEPVOL_N6DB (3 << 1) #define BEEPVOL_N3DB (4 << 1) #define BEEPVOL_0DB (5 << 1) #define BEEPVOL_3DB (6 << 1) #define BEEPVOL_6DB (7 << 1) #define BEEPEN (1) // R44 REG_INPUT #define MBVSEL_0_9AVDD (0) // Default value #define MBVSEL_0_65AVDD (1 << 8) #define R2_2INPVGA (1 << 6) #define RIN2INPVGA (1 << 5) // Default value #define RIP2INPVGA (1 << 4) // Default value #define L2_2INPVGA (1 << 2) #define LIN2INPVGA (1 << 1) // Default value #define LIP2INPVGA (1) // Default value // R45 REG_LEFT_PGA_GAIN #define INPPGAUPDATE (1 << 8) #define INPPGAZCL (1 << 7) #define INPPGAMUTEL (1 << 6) // R46 REG_RIGHT_PGA_GAIN #define INPPGAZCR (1 << 7) #define INPPGAMUTER (1 << 6) // R45 - R46 #define INPPGAVOL_POS (0) #define INPPGAVOL_MASK (63) // R47 REG_LEFT_ADC_BOOST #define PGABOOSTL (1 << 8) // Default value #define L2_2BOOSTVOL_POS (4) #define L2_2BOOSTVOL_MASK (7) #define L2_2BOOSTVOL_DISABLED (0) // Default value #define L2_2BOOSTVOL_N12DB (1 << 4) #define L2_2BOOSTVOL_N9DB (2 << 4) #define L2_2BOOSTVOL_N6DB (3 << 4) #define L2_2BOOSTVOL_N3DB (4 << 4) #define L2_2BOOSTVOL_0DB (5 << 4) #define L2_2BOOSTVOL_3DB (6 << 4) #define L2_2BOOSTVOL_6DB (7 << 4) #define AUXL2BOOSTVOL_POS (0) #define AUXL2BOOSTVOL_MASK (7) #define AUXL2BOOSTVOL_DISABLED (0) // Default value #define AUXL2BOOSTVOL_N12DB (1) #define AUXL2BOOSTVOL_N9DB (2) #define AUXL2BOOSTVOL_N6DB (3) #define AUXL2BOOSTVOL_N3DB (4) #define AUXL2BOOSTVOL_0DB (5) #define AUXL2BOOSTVOL_3DB (6) #define AUXL2BOOSTVOL_6DB (7) // R48 REG_RIGHT_ADC_BOOST #define PGABOOSTR (1 << 8) // Default value #define R2_2BOOSTVOL_POS (4) #define R2_2BOOSTVOL_MASK (7) #define R2_2BOOSTVOL_DISABLED (0) // Default value #define R2_2BOOSTVOL_N12DB (1 << 4) #define R2_2BOOSTVOL_N9DB (2 << 4) #define R2_2BOOSTVOL_N6DB (3 << 4) #define R2_2BOOSTVOL_N3DB (4 << 4) #define R2_2BOOSTVOL_0DB (5 << 4) #define R2_2BOOSTVOL_3DB (6 << 4) #define R2_2BOOSTVOL_6DB (7 << 4) #define AUXR2BOOSTVOL_POS (0) #define AUXR2BOOSTVOL_MASK (7) #define AUXR2BOOSTVOL_DISABLED (0) // Default value #define AUXR2BOOSTVOL_N12DB (1) #define AUXR2BOOSTVOL_N9DB (2) #define AUXR2BOOSTVOL_N6DB (3) #define AUXR2BOOSTVOL_N3DB (4) #define AUXR2BOOSTVOL_0DB (5) #define AUXR2BOOSTVOL_3DB (6) #define AUXR2BOOSTVOL_6DB (7) // R49 REG_OUTPUT #define DACL2RMIX (1 << 6) #define DACR2LMIX (1 << 5) #define OUT4BOOST (1 << 4) #define OUT3BOOST (1 << 3) #define SPKBOOST (1 << 2) #define TSDEN (1 << 1) #define VROI (1) // R50 REG_LEFT_MIXER #define AUXLMIXVOL_POS (6) #define AUXLMIXVOL_MASK (7) #define AUXLMIXVOL_N15DB (0) // Default value #define AUXLMIXVOL_N12DB (1 << 6) #define AUXLMIXVOL_N9DB (2 << 6) #define AUXLMIXVOL_N6DB (3 << 6) #define AUXLMIXVOL_N3DB (4 << 6) #define AUXLMIXVOL_0DB (5 << 6) #define AUXLMIXVOL_3DB (6 << 6) #define AUXLMIXVOL_6DB (7 << 6) #define AUXL2LMIX (1 << 5) #define BYPLMIXVOL_POS (2) #define BYPLMIXVOL_MASK (7) #define BYPLMIXVOL_N15DB (0) // Default value #define BYPLMIXVOL_N12DB (1 << 2) #define BYPLMIXVOL_N9DB (2 << 2) #define BYPLMIXVOL_N6DB (3 << 2) #define BYPLMIXVOL_N3DB (4 << 2) #define BYPLMIXVOL_0DB (5 << 2) #define BYPLMIXVOL_3DB (6 << 2) #define BYPLMIXVOL_6DB (7 << 2) #define BYPL2LMIX (1 << 1) #define DACL2LMIX (1) // R51 REG_RIGHT_MIXER #define AUXRMIXVOL_POS (6) #define AUXRMIXVOL_MASK (7) #define AUXRMIXVOL_N15DB (0) // Default value #define AUXRMIXVOL_N12DB (1 << 6) #define AUXRMIXVOL_N9DB (2 << 6) #define AUXRMIXVOL_N6DB (3 << 6) #define AUXRMIXVOL_N3DB (4 << 6) #define AUXRMIXVOL_0DB (5 << 6) #define AUXRMIXVOL_3DB (6 << 6) #define AUXRMIXVOL_6DB (7 << 6) #define AUXR2RMIX (1 << 5) #define BYPRMIXVOL_POS (2) #define BYPRMIXVOL_MASK (7) #define BYPRMIXVOL_N15DB (0) // Default value #define BYPRMIXVOL_N12DB (1 << 2) #define BYPRMIXVOL_N9DB (2 << 2) #define BYPRMIXVOL_N6DB (3 << 2) #define BYPRMIXVOL_N3DB (4 << 2) #define BYPRMIXVOL_0DB (5 << 2) #define BYPRMIXVOL_3DB (6 << 2) #define BYPRMIXVOL_6DB (7 << 2) #define BYPR2RMIX (1 << 1) #define DACR2RMIX (1) // R52 - R55 REG_LOUT1_VOL - REG_ROUT2_VOL #define HPVU (1 << 8) #define SPKVU (1 << 8) #define LOUT1ZC (1 << 7) #define LOUT1MUTE (1 << 6) #define ROUT1ZC (1 << 7) #define ROUT1MUTE (1 << 6) #define LOUT2ZC (1 << 7) #define LOUT2MUTE (1 << 6) #define ROUT2ZC (1 << 7) #define ROUT2MUTE (1 << 6) #define VOL_POS (0) #define VOL_MASK (63) // R56 REG_OUT3_MIXER #define OUT3MUTE (1 << 6) #define OUT4_2OUT3 (1 << 3) #define BYPL2OUT3 (1 << 2) #define LMIX2OUT3 (1 << 1) #define LDAC2OUT3 (1) // R57 REG_OUT4_MIXER #define OUT4MUTE (1 << 6) #define HALFSIG (1 << 5) #define LMIX2OUT4 (1 << 4) #define LDAC2OUT4 (1 << 3) #define BYPR2OUT4 (1 << 2) #define RMIX2OUT4 (1 << 1) #define RDAC2OUT4 (1) static rt_uint16_t wm8978_regval_tbl[58] = { 0X0000, 0X0000, 0X0000, 0X0000, 0X0050, 0X0000, 0X0140, 0X0000, 0X0000, 0X0000, 0X0000, 0X00FF, 0X00FF, 0X0000, 0X0100, 0X00FF, 0X00FF, 0X0000, 0X012C, 0X002C, 0X002C, 0X002C, 0X002C, 0X0000, 0X0032, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, 0X0038, 0X000B, 0X0032, 0X0000, 0X0008, 0X000C, 0X0093, 0X00E9, 0X0000, 0X0000, 0X0000, 0X0000, 0X0003, 0X0010, 0X0010, 0X0100, 0X0100, 0X0002, 0X0001, 0X0001, 0X0039, 0X0039, 0X0039, 0X0039, 0X0001, 0X0001 }; static void wm8978_write_reg(struct rt_i2c_bus_device *dev, rt_uint16_t s_data) { struct rt_i2c_msg msg; rt_uint8_t send_buffer[2]; RT_ASSERT(dev != RT_NULL); /* store temp */ wm8978_regval_tbl[s_data >> 9] = s_data & 0x1FF; send_buffer[0] = (rt_uint8_t)(s_data >> 8); send_buffer[1] = (rt_uint8_t)(s_data); msg.addr = 0x1A; msg.flags = RT_I2C_WR; msg.len = 2; msg.buf = send_buffer; rt_i2c_transfer(dev, &msg, 1); } static rt_uint16_t wm8978_read_reg(struct rt_i2c_bus_device *dev, rt_uint16_t reg) { return wm8978_regval_tbl[reg >> 9]; } /** * @brief Init WM8978 Codec device. * @param dev: I2C device handle * @retval RT_EOK if correct communication, else wrong communication */ void wm8978_player_start(struct rt_i2c_bus_device *dev) { wm8978_reset(dev); /* 1.5x boost power up sequence,Mute all outputs. */ wm8978_write_reg(dev, REG_LOUT1_VOL | LOUT1MUTE); wm8978_write_reg(dev, REG_ROUT1_VOL | ROUT1MUTE); wm8978_write_reg(dev, REG_LOUT2_VOL | LOUT2MUTE); wm8978_write_reg(dev, REG_ROUT2_VOL | ROUT2MUTE); /* Enable unused output chosen from L/ROUT2, OUT3 or OUT4. */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | OUT4EN); /* Set BUFDCOPEN=1, BIASEN=1 and BUFIOEN=1 in register R1 */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | BIASEN); /* Set SPKBOOST=1 in register R49. */ wm8978_write_reg(dev, REG_OUTPUT | SPKBOOST); /* Set VMIDSEL[1:0] to required value in register R1. */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); /* Set L/RMIXEN=1 and DACENL/R=1 in register R3.*/ wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR); /* Set BIASEN=1 in register R1. */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); /* Set L/ROUT2EN=1 in register R3. */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN); /* Enable other outputs as required. */ wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR); wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR | ADCENL | ADCENR); /* Digital inferface setup. */ wm8978_write_reg(dev, REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S); wm8978_write_reg(dev, REG_ADDITIONAL | WM_SR_8KHZ); wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | MICBEN | BIASEN); wm8978_write_reg(dev, REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1); /* Enable DAC 128x oversampling. */ wm8978_write_reg(dev, REG_DAC | DACOSR128); /* Set LOUT2/ROUT2 in BTL operation. */ wm8978_write_reg(dev, REG_BEEP | INVROUT2); wm8978_DAC_enabled(dev, 1); /* Set output volume. */ wm8978_set_volume(dev, 50); } void wm8978_record_start(struct rt_i2c_bus_device *dev) { wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | MICBEN | BIASEN | VMIDSEL_5K); wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | ROUT1EN | LOUT1EN | BOOSTENR | BOOSTENL); wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LOUT2EN | ROUT2EN | RMIXEN | LMIXEN); /* mclk be supplied by outside */ wm8978_write_reg(dev, REG_CLOCK_GEN); wm8978_write_reg(dev, (REG_BEEP | BEEPVOL_N3DB)); wm8978_write_reg(dev, (REG_LEFT_ADC_BOOST | PGABOOSTL)); wm8978_write_reg(dev, (REG_RIGHT_ADC_BOOST | PGABOOSTR)); wm8978_write_reg(dev, (REG_OUTPUT | TSDEN | SPKBOOST)); wm8978_write_reg(dev, (REG_DAC | RMIXEN)); wm8978_write_reg(dev, (REG_ADC | ADCOSR128)); wm8978_ADC_enabled(dev, 1); wm8978_DAC_enabled(dev, 0); wm8978_mic_enabled(dev, 1); wm8978_linein_enabled(dev, 1); wm8978_aux_enabled(dev, 0); wm8978_output_set(dev, 0, 0); wm8978_aux_gain(dev, 5); wm8978_mic_gain(dev, 50); } rt_err_t wm8978_init(struct rt_i2c_bus_device *dev) { wm8978_reset(dev); wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | MICBEN | BIASEN | VMIDSEL_5K); wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | ROUT1EN | LOUT1EN | BOOSTENR | BOOSTENL); wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LOUT2EN | ROUT2EN | RMIXEN | LMIXEN); /* mclk be supplied by outside */ wm8978_write_reg(dev, REG_CLOCK_GEN); wm8978_write_reg(dev, (REG_BEEP | BEEPVOL_N3DB)); wm8978_write_reg(dev, (REG_LEFT_ADC_BOOST | PGABOOSTL)); wm8978_write_reg(dev, (REG_RIGHT_ADC_BOOST | PGABOOSTR)); wm8978_write_reg(dev, (REG_OUTPUT | TSDEN | SPKBOOST)); wm8978_write_reg(dev, (REG_DAC | RMIXEN)); wm8978_write_reg(dev, (REG_ADC | ADCOSR128)); wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16); wm8978_mic_enabled(dev, 0); return RT_EOK; } void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) { rt_uint16_t value; value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT3); bool ? (value |= 3) : (value &= ~3); wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | value); } void wm8978_ADC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) { rt_uint16_t value; value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT2); bool ? (value |= 3) : (value &= ~3); wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | value); } void wm8978_mic_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) { rt_uint16_t value; value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT2); bool ? (value |= 3 << 2) : (value &= ~(3 << 2)); wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | value); value = wm8978_read_reg(dev, REG_INPUT); bool ? (value |= 3 << 4 | 3) : (value &= ~(3 << 4 | 3)); wm8978_write_reg(dev, REG_INPUT | value); } void wm8978_linein_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value) { rt_uint16_t regval; value &= 0x7; /* set left boost */ regval = wm8978_read_reg(dev, REG_LEFT_ADC_BOOST); regval &= ~(7 << 4); wm8978_write_reg(dev, REG_LEFT_ADC_BOOST | regval | value << 4); /* set right boost */ regval = wm8978_read_reg(dev, REG_RIGHT_ADC_BOOST); regval &= ~(7 << 4); wm8978_write_reg(dev, REG_RIGHT_ADC_BOOST | regval | value << 4); } void wm8978_aux_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value) { rt_uint16_t regval; value &= 0x7; /* set left boost */ regval = wm8978_read_reg(dev, REG_LEFT_ADC_BOOST); regval &= ~(7 << 0); wm8978_write_reg(dev, REG_LEFT_ADC_BOOST | regval | value << 0); /* set right boost */ regval = wm8978_read_reg(dev, REG_RIGHT_ADC_BOOST); regval &= ~(7 << 0); wm8978_write_reg(dev, REG_RIGHT_ADC_BOOST | regval | value << 0); } void wm8978_mic_gain(struct rt_i2c_bus_device *dev, rt_uint8_t gain) { gain &= 0X3F; wm8978_write_reg(dev, REG_LEFT_PGA_GAIN | gain); wm8978_write_reg(dev, REG_RIGHT_PGA_GAIN | gain | 1 << 8); } void wm8978_linein_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) { wm8978_linein_gain(dev, (bool ? L2_2BOOSTVOL_0DB : 0)); } void wm8978_aux_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) { wm8978_linein_gain(dev, (bool ? AUXL2BOOSTVOL_6DB : 0)); } void wm8978_output_set(struct rt_i2c_bus_device *dev, rt_bool_t dacen, rt_bool_t bypass) { rt_uint16_t regval = 0; if (dacen) { regval |= 1 << 0; } if (bypass) { regval |= 1 << 1; regval |= 5 << 2; } wm8978_write_reg(dev, REG_LEFT_MIXER | regval); wm8978_write_reg(dev, REG_RIGHT_MIXER | regval); } void wm8978_hpvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume) { volume &= 0X3F; if (volume == 0) { volume |= 1 << 6;//mute mode } wm8978_write_reg(dev, REG_LOUT1_VOL | volume); wm8978_write_reg(dev, REG_ROUT1_VOL | volume | (1 << 8)); } void wm8978_spkvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume) { volume &= 0X3F; if (volume == 0) { volume |= 1 << 6;//mute mode } wm8978_write_reg(dev, REG_LOUT2_VOL | volume); wm8978_write_reg(dev, REG_ROUT2_VOL | volume | (1 << 8)); } /** * @brief Set WM8978 DAC volume level. * @param dev: I2C device handle * @param vol: volume level(0 ~ 99) * @retval RT_EOK if correct communication, else wrong communication */ int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol) { vol = 63 * vol / 100; vol = (vol & VOL_MASK) << VOL_POS; wm8978_write_reg(dev, REG_LOUT1_VOL | vol); wm8978_write_reg(dev, REG_ROUT1_VOL | HPVU | vol); wm8978_write_reg(dev, REG_LOUT2_VOL | vol); wm8978_write_reg(dev, REG_ROUT2_VOL | SPKVU | vol); return RT_EOK; } void wm8978_interface_cfg(struct rt_i2c_bus_device *dev, enum data_fomat_select fmt, rt_uint32_t bitBand) { rt_uint16_t temp = 0; switch (fmt) { case RIGHT_FOMAT_SELECT: temp = FMT_RIGHT_JUSTIFIED; break; case LEFT_FOMAT_SELECT: temp = FMT_LEFT_JUSTIFIED; break; case I2S_FOMAT_SELECT: temp = FMT_I2S; break; case PCM_FOMAT_SELECT: temp = FMT_PCM; break; default: break; } switch (bitBand) { case 16: temp |= WL_16BITS; break; case 20: temp |= WL_20BITS; break; case 24: temp |= WL_24BITS; break; case 32: temp |= WL_32BITS; break; default: break; } wm8978_write_reg(dev, REG_AUDIO_INTERFACE | temp); } void wm8978_reset(struct rt_i2c_bus_device *dev) { wm8978_write_reg(dev, REG_SOFTWARE_RESET); } void wm8978_mute_enabled(struct rt_i2c_bus_device *dev, rt_bool_t enable) { wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | (enable ? BIASEN : 0)); } rt_err_t wm8978_set_EQ1(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) { rt_uint16_t temp = 0; if (freq > 3 || gain > 24) { return -RT_ERROR; } switch (freq) { case 0: temp = EQ1C_80HZ; break; case 1: temp = EQ1C_105HZ; break; case 2: temp = EQ1C_135HZ; break; case 3: temp = EQ1C_175HZ; break; default: break; } /* 0 - 24 as -12~+12dB */ gain = 24 - gain; temp |= gain; wm8978_write_reg(dev, REG_EQ1 | temp); return RT_EOK; } rt_err_t wm8978_set_EQ2(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) { rt_uint16_t temp = 0; if (freq > 3 || gain > 24) { return -RT_ERROR; } switch (freq) { case 0: temp = EQ2C_230HZ; break; case 1: temp = EQ2C_300HZ; break; case 2: temp = EQ2C_385HZ; break; case 3: temp = EQ2C_500HZ; break; default: break; } /* 0 - 24 as -12~+12dB */ gain = 24 - gain; temp |= gain; wm8978_write_reg(dev, REG_EQ2 | temp); return RT_EOK; } rt_err_t wm8978_set_EQ3(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) { rt_uint16_t temp = 0; if (freq > 3 || gain > 24) { return -RT_ERROR; } switch (freq) { case 0: temp = EQ3C_650HZ; break; case 1: temp = EQ3C_850HZ; break; case 2: temp = EQ3C_1_1KHZ; break; case 3: temp = EQ3C_1_4KHZ; break; default: break; } /* 0 - 24 as -12~+12dB */ gain = 24 - gain; temp |= gain; wm8978_write_reg(dev, REG_EQ3 | temp); return RT_EOK; } rt_err_t wm8978_set_EQ4(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) { rt_uint16_t temp = 0; if (freq > 3 || gain > 24) { return -RT_ERROR; } switch (freq) { case 0: temp = EQ4C_1_8KHZ; break; case 1: temp = EQ4C_2_4KHZ; break; case 2: temp = EQ4C_3_2KHZ; break; case 3: temp = EQ4C_4_1KHZ; break; default: break; } /* 0 - 24 as -12~+12dB */ gain = 24 - gain; temp |= gain; wm8978_write_reg(dev, REG_EQ4 | temp); return RT_EOK; } rt_err_t wm8978_set_EQ5(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) { rt_uint16_t temp = 0; if (freq > 3 || gain > 24) { return -RT_ERROR; } switch (freq) { case 0: temp = EQ5C_5_3KHZ; break; case 1: temp = EQ5C_6_9KHZ; break; case 2: temp = EQ5C_9KHZ; break; case 3: temp = EQ5C_11_7KHZ; break; default: break; } /* 0 - 24 as -12~+12dB */ gain = 24 - gain; temp |= gain; wm8978_write_reg(dev, REG_EQ5 | temp); return RT_EOK; } void wm8978_3D_Set(struct rt_i2c_bus_device *dev, rt_uint8_t depth) { wm8978_write_reg(dev, REG_3D | (depth & 0xf)); } ``` 3、使用官方的audio的demo ```c #include <rtthread.h> #include <rtdevice.h> #include <dfs_file.h> #include <unistd.h> #include <board.h> #define BUFSZ 1024 #define SOUND_DEVICE_NAME "sound0" /* Audio 设备名称 */ static rt_device_t snd_dev; /* Audio 设备句柄 */ struct RIFF_HEADER_DEF { char riff_id[4]; // 'R','I','F','F' uint32_t riff_size; char riff_format[4]; // 'W','A','V','E' }; struct WAVE_FORMAT_DEF { uint16_t FormatTag; uint16_t Channels; uint32_t SamplesPerSec; uint32_t AvgBytesPerSec; uint16_t BlockAlign; uint16_t BitsPerSample; }; struct FMT_BLOCK_DEF { char fmt_id[4]; // 'f','m','t',' ' uint32_t fmt_size; struct WAVE_FORMAT_DEF wav_format; }; struct DATA_BLOCK_DEF { char data_id[4]; // 'R','I','F','F' uint32_t data_size; }; struct wav_info { struct RIFF_HEADER_DEF header; struct FMT_BLOCK_DEF fmt_block; struct DATA_BLOCK_DEF data_block; }; int wavplay_sample(int argc, char **argv) { int fd = -1; uint8_t *buffer = NULL; struct wav_info *info = NULL; struct rt_audio_caps caps = {0}; if (argc != 2) { rt_kprintf("Usage:\n"); rt_kprintf("wavplay_sample song.wav\n"); return 0; } fd = open(argv[1], O_RDONLY); if (fd < 0) { rt_kprintf("open file failed!\n"); goto __exit; } buffer = rt_malloc(BUFSZ); if (buffer == RT_NULL) goto __exit; info = (struct wav_info *) rt_malloc(sizeof * info); if (info == RT_NULL) goto __exit; if (read(fd, &(info->header), sizeof(struct RIFF_HEADER_DEF)) <= 0) goto __exit; if (read(fd, &(info->fmt_block), sizeof(struct FMT_BLOCK_DEF)) <= 0) goto __exit; if (read(fd, &(info->data_block), sizeof(struct DATA_BLOCK_DEF)) <= 0) goto __exit; rt_kprintf("wav information:\n"); rt_kprintf("FormatTag %d\n", info->fmt_block.wav_format.FormatTag);//编码格式 rt_kprintf("channel %d\n", info->fmt_block.wav_format.Channels);//声道数，单声道为1，双声道为2 rt_kprintf("samplerate %d\n", info->fmt_block.wav_format.SamplesPerSec);//采样频率即记录每秒取样数 rt_kprintf("AvgBytesPerSec %d\n", info->fmt_block.wav_format.AvgBytesPerSec);//记录每秒的数据量 rt_kprintf("BlockAlign %d\n", info->fmt_block.wav_format.BlockAlign);//记录区块的对齐单位 rt_kprintf("BitsPerSample %d\n", info->fmt_block.wav_format.BitsPerSample);//记录每个取样所需的位元数 rt_kprintf("datasize %d\n", info->data_block.data_size);//语音数据大小 rt_pin_mode(PIN_KEY_SOUND_PALY_EN, PIN_MODE_OUTPUT); rt_pin_write(PIN_KEY_SOUND_PALY_EN, ACTIVE_KEY_PIN_SOUND_PALY_EN); /* 根据设备名称查找 Audio 设备，获取设备句柄 */ snd_dev = rt_device_find(SOUND_DEVICE_NAME); /* 以只写方式打开 Audio 播放设备 */ rt_device_open(snd_dev, RT_DEVICE_OFLAG_WRONLY); /* 设置采样率、通道、采样位数等音频参数信息 */ caps.main_type = AUDIO_TYPE_OUTPUT; /* 输出类型（播放设备 ）*/ caps.sub_type = AUDIO_DSP_PARAM; /* 设置所有音频参数信息 */ caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; /* 采样率 */ caps.udata.config.channels = info->fmt_block.wav_format.Channels; /* 采样通道 */ caps.udata.config.samplebits = 16; /* 采样位数 */ rt_device_control(snd_dev, AUDIO_CTL_CONFIGURE, &caps); while (1) { int length; /* 从文件系统读取 wav 文件的音频数据 */ length = read(fd, buffer, BUFSZ); if (length <= 0) break; /* 向 Audio 设备写入音频数据 */ rt_device_write(snd_dev, 0, buffer, length); } /* 关闭 Audio 设备 */ rt_device_close(snd_dev); __exit: if (fd >= 0) close(fd); if (buffer) rt_free(buffer); if (info) rt_free(info); return 0; } MSH_CMD_EXPORT(wavplay_sample, play wav file); ``` 4、DMA的中断进去了以及串口数据，但是喇叭就是没有声音 
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2024-05-22
这家伙很懒，什么也没写！
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