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YAFFS
【新增】移植最新版yaffs2
发布于 2018-09-18 17:58:19 浏览:3063
订阅该版
[代码仓库](https://github.com/heyuanjie87/yaffs2_rtt_port.git) 本次移植采用了类似linux的mtd接口,写nand驱动会更简单。 测试结果: ``` msh />ls Directory /: 1.txt 6 222
lost+found
msh /> msh />dfdisk free: 4.1 MB [ 2108 block, 2048 bytes per block ] msh /> msh />cat 1.txt333333 msh /> msh />mv 222 333222 => 333 msh /> msh />rm 1.txt \ | /- RT - Thread Operating System / | \ 3.1.1 build Sep 18 2018 2006 - 2018 Copyright by rt-thread team msh />ls Directory /: 333
lost+found
``` k9f1g08驱动参考: ```c #include
#include
#define K9F1G_READID 0x90 #define K9F1G_RESET 0xFF #define K9F1G_PGAEREAD1 0x00 #define K9F1G_PAGEREAD2 0x30 #define K9F1G_RANDOMDATAOUTPUT1 0x05 #define K9F1G_RANDOMDATAOUTPUT2 0xE0 #define K9F1G_PAGEPROGRAM1 0x80 #define K9F1G_PAGEPROGRAM2 0x10 #define K9F1G_RANDOMDATAINPUT 0x85 #define K9F1G_BLOCKERASE1 0x60 #define K9F1G_BLOCKERASE2 0xD0 #define K9F1G_READSTATUS 0x70 #define K9F1G_CACHEPROGRAM1 0x80 #define K9F1G_CACHEPROGRAM2 0x15 #define K9F1G_COPYBACKREAD1 0x00 #define K9F1G_COPYBACKREAD2 0x35 #define K9F1G_COPYBACKPROGRAM1 0x85 #define K9F1G_COPYBACKPROGRAM2 0x10 #define K9F1G_BUSY (1<<6) #define K9F1G_OK (1<<0) #define MAX_VALIDBLOCK 900 #define SYS_HW_DFBASE 0x70000000 #define M8(adr) (*((volatile unsigned char *) (adr))) #define FLASH_CMD M8(SYS_HW_DFBASE + 0x10000) #define FLASH_ADR M8(SYS_HW_DFBASE + 0x20000) #define FLASH_DAT M8(SYS_HW_DFBASE + 0) #define FSMC_NWE_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_NWE_GPIO_X (GPIOD) #define FSMC_NWE_GPIO_PIN (GPIO_PIN_5) #define FSMC_NWE_GPIO_MODE (GPIO_Mode_AF) #define FSMC_NWE_GPIO_SPEED (GPIO_High_Speed) #define FSMC_NWE_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_NWE_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_NWE_GPIO_AF (GPIO_AF_FSMC) #define FSMC_NWE_GPIO_1OUT (GPIO_1OUT_HIGH) #define FSMC_NOE_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_NOE_GPIO_X (GPIOD) #define FSMC_NOE_GPIO_PIN (GPIO_PIN_4) #define FSMC_NOE_GPIO_MODE (GPIO_Mode_AF) #define FSMC_NOE_GPIO_SPEED (GPIO_High_Speed) #define FSMC_NOE_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_NOE_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_NOE_GPIO_AF (GPIO_AF_FSMC) #define FSMC_NOE_GPIO_1OUT (GPIO_1OUT_HIGH) #define FSMC_D0_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_D0_GPIO_X (GPIOD) #define FSMC_D0_GPIO_PIN (GPIO_PIN_14) #define FSMC_D0_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D0_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D0_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D0_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D0_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D0_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D1_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_D1_GPIO_X (GPIOD) #define FSMC_D1_GPIO_PIN (GPIO_PIN_15) #define FSMC_D1_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D1_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D1_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D1_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D1_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D1_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D2_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_D2_GPIO_X (GPIOD) #define FSMC_D2_GPIO_PIN (GPIO_PIN_0) #define FSMC_D2_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D2_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D2_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D2_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D2_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D2_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D3_GPIO_RCC (RCC_AHB1Periph_GPIOD) #define FSMC_D3_GPIO_X (GPIOD) #define FSMC_D3_GPIO_PIN (GPIO_PIN_1) #define FSMC_D3_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D3_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D3_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D3_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D3_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D3_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D4_GPIO_RCC (RCC_AHB1Periph_GPIOE) #define FSMC_D4_GPIO_X (GPIOE) #define FSMC_D4_GPIO_PIN (GPIO_PIN_7) #define FSMC_D4_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D4_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D4_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D4_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D4_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D4_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D5_GPIO_RCC (RCC_AHB1Periph_GPIOE) #define FSMC_D5_GPIO_X (GPIOE) #define FSMC_D5_GPIO_PIN (GPIO_PIN_8) #define FSMC_D5_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D5_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D5_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D5_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D5_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D5_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D6_GPIO_RCC (RCC_AHB1Periph_GPIOE) #define FSMC_D6_GPIO_X (GPIOE) #define FSMC_D6_GPIO_PIN (GPIO_PIN_9) #define FSMC_D6_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D6_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D6_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D6_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D6_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D6_GPIO_1OUT (GPIO_1OUT_LOW) #define FSMC_D7_GPIO_RCC (RCC_AHB1Periph_GPIOE) #define FSMC_D7_GPIO_X (GPIOE) #define FSMC_D7_GPIO_PIN (GPIO_PIN_10) #define FSMC_D7_GPIO_MODE (GPIO_Mode_AF) #define FSMC_D7_GPIO_SPEED (GPIO_High_Speed) #define FSMC_D7_GPIO_PULL (GPIO_PuPd_NOPULL) #define FSMC_D7_GPIO_OTYPE (GPIO_OType_PP) #define FSMC_D7_GPIO_AF (GPIO_AF_FSMC) #define FSMC_D7_GPIO_1OUT (GPIO_1OUT_LOW) static void fsmc_nand_init(void) { FSMC_NAND_PCCARDTimingInitTypeDef pFSMC_NAND_PCCARDTiming; FSMC_NANDInitTypeDef FSMC_NANDInitStructure; RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); pFSMC_NAND_PCCARDTiming.FSMC_SetupTime = 0x02; pFSMC_NAND_PCCARDTiming.FSMC_WaitSetupTime = 0x06; pFSMC_NAND_PCCARDTiming.FSMC_HoldSetupTime = 0x04; pFSMC_NAND_PCCARDTiming.FSMC_HiZSetupTime = 0x02; FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Disable; FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00; FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00; FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &pFSMC_NAND_PCCARDTiming; FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &pFSMC_NAND_PCCARDTiming; FSMC_NANDDeInit(FSMC_Bank2_NAND); FSMC_NANDInit(&FSMC_NANDInitStructure); FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE); } static void fsmc_gpio_init(void) { GPIO_InitTypeDef GPIO_InitStructure; /* Enable GPIOs clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE, ENABLE); GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_Init(GPIOE, &GPIO_InitStructure); /* NAND_R/B: PD6 */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC); /* NCS */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC); /* GPIO Data Line configuration */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); //D0 GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); //D1 GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); //D2 GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); //D3 GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC); //D4 GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC); //D5 GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC); //D6 GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC); //D7 GPIO_PinAFConfig(GPIOD, GPIO_PinSource11 , GPIO_AF_FSMC); //A16 GPIO_PinAFConfig(GPIOD, GPIO_PinSource12 , GPIO_AF_FSMC); //A17 /* NOE configuration */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); /* NWE configuration */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); } rt_inline void nwait (void) { while(GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == 0); } rt_inline uint8_t nstatus(void) { FLASH_CMD = K9F1G_READSTATUS; return FLASH_DAT; } rt_inline void naddr(rt_uint8_t addr) { FLASH_ADR = addr; } rt_inline void ncmd(rt_uint8_t cmd) { FLASH_CMD = cmd; } rt_inline uint8_t nread8(void) { return FLASH_DAT; } rt_inline void nwrite8(uint8_t dat) { FLASH_DAT = dat; } rt_inline void io_readbuf(uint8_t *buf, int size) { while (size) { *buf = nread8(); buf ++; size --; } } rt_inline void io_writebuf(const uint8_t *buf, int size) { while (size) { nwrite8(*buf); buf ++; size --; } } rt_inline int k9f2g08_erase(int page) { ncmd(K9F1G_BLOCKERASE1); naddr(page); naddr(page >> 8); ncmd(K9F1G_BLOCKERASE2); nwait(); return nstatus(); } static int k9f2g08_read_buf(rt_nand_t *nand, uint8_t *buf, int len) { io_readbuf(buf, len); return 0; } static int k9f2g08_write_buf(rt_nand_t *nand, const uint8_t *buf, int len) { io_writebuf(buf, len); return 0; } static int k9f2g08_cmdfunc(rt_nand_t *nand, int cmd, int page, int offset) { int ret = 0; switch (cmd) { case NAND_CMD_PAGE_RD: { ncmd(K9F1G_PGAEREAD1); naddr(offset); naddr(offset >> 8); naddr(page); naddr(page >> 8); ncmd(K9F1G_PAGEREAD2); nwait(); ncmd(K9F1G_PGAEREAD1); }break; case NAND_CMD_PAGE_WR0: { ncmd(K9F1G_PAGEPROGRAM1); naddr(offset); naddr(offset >> 8); naddr(page); naddr(page >> 8); }break; case NAND_CMD_PAGE_WR1: { ncmd(K9F1G_PAGEPROGRAM2); nwait(); ret = nstatus() & 0x01; }break; case NAND_CMD_BLK_ERASE: { ret = k9f2g08_erase(page); }break; case NAND_CMD_ECC_EN: { FSMC_NANDECCCmd(FSMC_Bank2_NAND, ENABLE); }break; case NAND_CMD_ECC_DIS: { FSMC_NANDECCCmd(FSMC_Bank2_NAND,DISABLE); }break; } return ret; } static void stm32_calc_ecc(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc) { uint32_t e; e = FSMC_GetECC(FSMC_Bank2_NAND); ecc[0] = e; ecc[1] = e >> 8; ecc[2] = e >> 16; } static int stm32_correct(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { unsigned int diff0, diff1, diff2; unsigned int bit, byte; diff0 = read_ecc[0] ^ calc_ecc[0]; diff1 = read_ecc[1] ^ calc_ecc[1]; diff2 = read_ecc[2] ^ calc_ecc[2]; if (diff0 == 0 && diff1 == 0 && diff2 == 0) return 0; /* ECC is ok */ /* sometimes people do not think about using the ECC, so check * to see if we have an 0xff,0xff,0xff read ECC and then ignore * the error, on the assumption that this is an un-eccd page. */ if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff) return 0; /* Can we correct this ECC (ie, one row and column change). * Note, this is similar to the 256 error code on smartmedia */ if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { /* calculate the bit position of the error */ bit = ((diff2 >> 3) & 1) | ((diff2 >> 4) & 2) | ((diff2 >> 5) & 4); /* calculate the byte position of the error */ byte = ((diff2 << 7) & 0x100) | ((diff1 << 0) & 0x80) | ((diff1 << 1) & 0x40) | ((diff1 << 2) & 0x20) | ((diff1 << 3) & 0x10) | ((diff0 >> 4) & 0x08) | ((diff0 >> 3) & 0x04) | ((diff0 >> 2) & 0x02) | ((diff0 >> 1) & 0x01); dat[byte] ^= (1 << bit); return 0; } /* if there is only one bit difference in the ECC, then * one of only a row or column parity has changed, which * means the error is most probably in the ECC itself */ diff0 |= (diff1 << 8); diff0 |= (diff2 << 16); /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */ if ((diff0 & (diff0 - 1)) == 0) return 1; return -1; } static rt_nand_t _nand0; static const struct nand_ops _ops = { k9f2g08_cmdfunc, k9f2g08_read_buf, k9f2g08_write_buf, 0, 0 }; static const struct mtd_part _parts[2] = { {"nand0", 0, 1024*1024*10}, {"nand1", 2048*64*4 + 1024*1024*10, 1024*1024*10} }; static const struct mtd_oob_region _layout[2] = { {2, 38}, //free {40, 24} //ecc }; int stm32_nand_init(void) { rt_nand_t *nand; fsmc_gpio_init(); fsmc_nand_init(); nand = &_nand0; nand->freelayout = &_layout[0]; nand->ecc.mode = NAND_ECCM_HW; nand->ecc.bytes = 3; nand->ecc.stepsize = 256; nand->ecc.layout = &_layout[1]; nand->ecc.calculate = stm32_calc_ecc; nand->ecc.correct = stm32_correct; nand->ops = &_ops; rt_mtd_nand_init(nand, 2048*64, 2048, 1024, 64); rt_mtd_register(&nand->parent, _parts, 2); return 0; } INIT_DEVICE_EXPORT(stm32_nand_init); ```
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默认排序
按发布时间排序
hcb900330
2018-12-22
这家伙很懒,什么也没写!
大神,文件系统挂上去效果怎么样啊?我用的rtt还是2.1的 nandflash是k9f2g08 用的uffs坑死了
heyuanjie87
2018-12-22
这家伙很懒,什么也没写!
我也只做过简单的测试,可以用还没被坑
tsx1983
2018-12-23
这家伙很懒,什么也没写!
>大神,文件系统挂上去效果怎么样啊?我用的rtt还是2.1的 nandflash是k9f2g08 用的uffs坑死了 ... --- uffs如何坑了?
tsx1983
2018-12-23
这家伙很懒,什么也没写!
我也测试了下yaffs,简单的文件读写测试,一般情况下没问题.但偶尔蹦出来读写不一致的情况,不知是文件系统问题还是内存问题。但是在yaffs上跑sqlite,和uffs一样,会出SQL error: database disk image is malformed错误,不知道什么鬼。 在SD卡上测试同样的例程则不会
jianfeii
2019-06-17
这家伙很懒,什么也没写!
有完整的代码可以参考么?
出出啊
2021-06-20
恃人不如自恃,人之为己者不如己之自为也
您好,我现在想移植yaffs2到`nand flash`上面,执行到`yaffs_start_up` 后面不知道怎么操作了,怎么把`flash`分区挂载到`“/”`目录呢? 请指教,谢谢!
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