RT-Thread-XMC7200_EVK实践-ETHRT-Thread问答社区

XMC7200_EVK实践-ETH

发布于 2024-08-20 22:45:15 浏览：412 订阅该版

[tocm]

# 00 前言
很高兴入选了这次测评活动，平时喜欢尝鲜新出的板卡，这是第一次接触英飞凌家的板子和生态，收获不小，在此感谢RTT和厂家。
XMC7200是英飞凌推出的一款32位**双核**MCU子系统（ARM Cortex-M7 和 ARM Cortex-M0），集成了多达两个 350MHz Arm® Cortex-M7® 作为主应用处理器，一个 100MHz Arm® Cortex-M0®+ ，支持百兆和**千兆**以太网。

官方主页：[xmc7200](https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/32-bit-xmc7000-industrial-microcontroller-arm-cortex-m7/xmc7200-e272k8384aa/ "xmc7200")

KIT_XMC72_EVK开发板主页：[KIT_XMC72_EVK](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc72_evk/ "KIT_XMC72_EVK")

# 01官方工具安装
英飞凌烧录工具——Cypress programmer
英飞凌官方IDE——ModusToolbox
Keil_MDK && ENV环境（使用主线代码，需要下载ENV2.0）

# 02生成以太网示例工程
使用ModusToolBox生成TCP Client示例工程，该工程包含了我们需要的以太网驱动配置。由于墙的原因，一次下载可能不成功，需要耐心多尝试几次。
选择TCP例程：
![1.png](https://oss-club.rt-thread.org/uploads/20240820/aa5984e904da250e2eca5ba682994494.png.webp)

平台选择KEIL MDK：
![2.png](https://oss-club.rt-thread.org/uploads/20240820/5d2d2992483ac4ed08a76ca4b758a2cf.png.webp)

通过分析该示例，可以知道，应用层主要是调用ECM接口实现网络相关功能，ECM接口主要是调用了cy_ephy和cy_ethif两个驱动，实现了phy芯片dp83867ir的驱动，如何使用以太网和phy驱动，头文件里面将步骤描述的十分详细：
![4.png](https://oss-club.rt-thread.org/uploads/20240820/25ac94c2b654ee282d6e4cf67f30800d.png.webp)

# 03移植以太网驱动到RTT
以太网驱动移植步骤主要参考文档中心[https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/components/network/an0010-lwip-driver-porting](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/components/network/an0010-lwip-driver-porting)
XMC7200带 MAC（以太网媒体接入控制器 ），通过 RGMII 接口和PHY芯片（物理接口收发器 ） DP83867IR通信。

使用ETH1外设连接了PHY芯片:
![3.png](https://oss-club.rt-thread.org/uploads/20240820/b2a406bae99fe0bf2ff8b24f96dc8a65.png.webp)

RT-Thread 网络设备继承了标准设备，是由 eth_device 结构体定义的，我们需要填充该结构：

```c
struct eth_device
{
    /* 标准设备 */
    struct rt_device parent;

/* lwIP 网络接口 */
    struct netif *netif;
    /* 发送应答信号量 */
    struct rt_semaphore tx_ack;

/* 网络状态标志 */
    rt_uint16_t flags;
    rt_uint8_t  link_changed;
    rt_uint8_t  link_status;

/* 数据包收发接口 */
    struct pbuf* (*eth_rx)(rt_device_t dev);
    rt_err_t (*eth_tx)(rt_device_t dev, struct pbuf* p);
};
```
驱动都是类似的，这里我们直接使用stm32 bsp里面的以太网驱动作为模板，在其基础上修改，以适配XMC7200，rtconfig.h关于网络内容如下（由于长度限制，完整文件内容见附件）：

```c
/* Network */

#define RT_USING_SAL

/* Docking with protocol stacks */

#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_SOCKETS_NUM 16
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP203
#define RT_USING_LWIP_VER_NUM 0x20003
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
//#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1

/* Static IPv4 Address */

#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define LWIP_NO_RX_THREAD
#define RT_LWIP_ETHTHREAD_PRIORITY 21
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */

#define BSP_USING_ETH
```

drv_eth.h内容如下：

```c
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__

#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>

#define PHY_USING_DP83867

#if defined(PHY_USING_DP83867)
#define PHY_Status_REG              0x10U
#define PHY_10M_MASK                (1<<1)
#define PHY_FULL_DUPLEX_MASK        (1<<2)
#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
#define PHY_Status_SPEED_100M(sr)   (!PHY_Status_SPEED_10M(sr))
#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
/*  The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG      0x12U
#define PHY_LINK_CHANGE_FLAG        (1<<13)
/*  The PHY interrupt control register. */
#define PHY_INTERRUPT_CTRL_REG      0x11U
#define PHY_INTERRUPT_EN            ((1<<0)|(1<<1))
/*  The PHY interrupt mask register. */
#define PHY_INTERRUPT_MASK_REG      0x12U
#define PHY_INT_MASK                (1<<5)
#endif

#define CY_IP_MXETH 1
#define ETH_INTERFACE_TYPE ETH1

/* After hardware initialization, max wait time to get the physical link up */
#define MAX_WAIT_ETHERNET_PHY_STATUS          (10000)

#define REGISTER_ADDRESS_PHY_REG_BMCR       PHYREG_00_BMCR          /* BMCR register (0x0000) to read the speed and duplex mode */
#define REGISTER_PHY_REG_DUPLEX_MASK        PHYBMCR_FULL_DUPLEX_Msk /* Bit 8 of BMCR register to read the duplex mode */
#define REGISTER_PHY_REG_SPEED_MASK         (0x2040)                /* Bit 6, 13: BMCR register to read the speed */
#define REGISTER_PHY_REG_SPEED_MASK_10M     (0x0000)                /* Bit 6, 13: Both are set to 0 for 10M speed */
#define REGISTER_PHY_REG_SPEED_MASK_100M    (0x2000)                /* Bit 6, 13: Set to 0 and 1 respectively for 100M speed */
#define REGISTER_PHY_REG_SPEED_MASK_1000M   (0x0040)                /* Bit 6, 13: Set to 1 and 0 respectively for 1000M speed */

。。。

cy_rslt_t  cy_eth_driver_initialization(ETH_Type *eth_type, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj);
void deregister_cb(ETH_Type *reg_base);

#endif /* __DRV_ETH_H__ */

```

drv_eth.c内容如下：

```c
#include "drv_eth.h"
#include <netif/ethernetif.h>
#include <lwipopts.h>

#include "cy_ethif.h"
#include "cy_ephy.h"

struct rt_stm32_eth
{
    struct eth_device parent;
#ifndef PHY_USING_INTERRUPT_MODE
    rt_timer_t poll_link_timer;
#endif
    rt_uint8_t  dev_addr[MAX_ADDR_LEN];
    rt_uint32_t    ETH_Speed;
    rt_uint32_t    ETH_Mode;
};

/** Interrupt configurations    */
static cy_stc_ethif_intr_config_t stcInterruptConfig = {
                .btsu_time_match        = 0,          /** Timestamp unit time match event */
                .bwol_rx                = 0,          /** Wake-on-LAN event received */
                .blpi_ch_rx             = 0,          /** LPI indication status bit change received */
                .btsu_sec_inc           = 0,          /** TSU seconds register increment */
                .bptp_tx_pdly_rsp       = 0,          /** PTP pdelay_resp frame transmitted */
                .bptp_tx_pdly_req       = 0,          /** PTP pdelay_req frame transmitted */
                .bptp_rx_pdly_rsp       = 0,          /** PTP pdelay_resp frame received */
                .bptp_rx_pdly_req       = 0,          /** PTP pdelay_req frame received */
                .bptp_tx_sync           = 0,          /** PTP sync frame transmitted */
                .bptp_tx_dly_req        = 0,          /** PTP delay_req frame transmitted */
                .bptp_rx_sync           = 0,          /** PTP sync frame received */
                .bptp_rx_dly_req        = 0,          /** PTP delay_req frame received */
                .bext_intr              = 0,          /** External input interrupt detected */
                .bpause_frame_tx        = 0,          /** Pause frame transmitted */
                .bpause_time_zero       = 0,          /** Pause time reaches zero or zero pause frame received */
                .bpause_nz_qu_rx        = 0,          /** Pause frame with non-zero quantum received */
                .bhresp_not_ok          = 0,          /** DMA HRESP not OK */
                .brx_overrun            = 1,          /** Rx overrun error 1*/
                .bpcs_link_change_det   = 0,          /** Link status change detected by PCS */
                .btx_complete           = 1,          /** Frame has been transmitted successfully 1*/
                .btx_fr_corrupt         = 0,          /** Tx frame corrupted */
                .btx_retry_ex_late_coll = 1,          /** Retry limit exceeded or late collision 1*/
                .btx_underrun           = 1,          /** Tx underrun 1*/
                .btx_used_read          = 1,          /** Used bit set has been read in Tx descriptor list 1*/
                .brx_used_read          = 1,          /** Used bit set has been read in Rx descriptor list 1*/
                .brx_complete           = 1,          /** Frame received successfully and stored 1*/
                .bman_frame             = 0,          /** Management frame sent */
};

static cy_stc_ethif_cb_t stcInterruptCB = {
                .rxframecb  = cy_process_ethernet_data_cb,
                .txerrorcb  = cy_tx_failure_cb,
                .txcompletecb = cy_tx_complete_cb,
                .tsuSecondInccb = NULL,
                .rxgetbuff = cy_notify_ethernet_rx_data_cb
};

/** Enable Ethernet interrupts  */
static const cy_stc_sysint_t irq_cfg_ethx_q0 = {.intrSrc  = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC),    .intrPriority=3UL};
static const cy_stc_sysint_t irq_cfg_ethx_q1 = {.intrSrc  = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC_Q1), .intrPriority=3UL};
static const cy_stc_sysint_t irq_cfg_ethx_q2 = {.intrSrc  = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC_Q2), .intrPriority=3UL};

/********************************************************/
/** Interrupt handlers for Ethernet 1     */
static void Cy_Ethx_InterruptHandler (void)
{
    rt_interrupt_enter();
    Cy_ETHIF_DecodeEvent(ETH_REG_BASE);
    rt_interrupt_leave();
}

cy_rslt_t cy_eth_driver_initialization(ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj)
{
    cy_rslt_t result = CY_RSLT_SUCCESS;
    uint32_t retry_count = 0;

/* Configure Ethernet port pins */
    ethernet_portpins_init();

rt_kprintf("eth gpio init\n");

Cy_SysInt_Init(&irq_cfg_ethx_q0, Cy_Ethx_InterruptHandler);
    Cy_SysInt_Init(&irq_cfg_ethx_q1, Cy_Ethx_InterruptHandler);
    Cy_SysInt_Init(&irq_cfg_ethx_q2, Cy_Ethx_InterruptHandler);

NVIC_ClearPendingIRQ(NvicMux3_IRQn);
    NVIC_EnableIRQ(NvicMux3_IRQn);

/* rx Q0 buffer pool */
    stcENETConfig.pRxQbuffPool[0] = (cy_ethif_buffpool_t *)&pRx_Q_buff_pool;
    stcENETConfig.pRxQbuffPool[1] = NULL;

/** Initialize PHY  */
    init_phy_DP83867IR(reg_base, ecm_phy_config, phy_obj);

while( retry_count < MAX_WAIT_ETHERNET_PHY_STATUS)
    {
        rt_kprintf("waitting Link up...\n");
        if (Cy_EPHY_GetLinkStatus(phy_obj) == 1UL)
        {
            rt_kprintf("=== Link up ok ===\n");
            result = CY_RSLT_SUCCESS;
            break;
        }
        rt_thread_mdelay(SLEEP_ETHERNET_PHY_STATUS);
        retry_count += SLEEP_ETHERNET_PHY_STATUS;
    }

if(retry_count > MAX_WAIT_ETHERNET_PHY_STATUS)
    {
        rt_kprintf("phy err Link up failed\n");
    }

Cy_ETHIF_RegisterCallbacks(reg_base, &stcInterruptCB);

return result;
}

static __attribute__((aligned(4))) rt_uint8_t mempool[10][CY_ETH_SIZE_MAX_FRAME];
volatile int mp_index = 0;
uint8_t *pp = NULL;
void cy_notify_ethernet_rx_data_cb(ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length)
{
     rt_kprintf("==notice rx\n");
    pp = (uint8_t*)mempool[mp_index];
    *u32Length = CY_ETH_SIZE_MAX_FRAME;
    *u8RxBuffer = pp;
    mp_index++;
    if(mp_index>=8)
    {
        mp_index=0;
    }
    return;
}

void cy_process_ethernet_data_cb(ETH_Type *eth_type, uint8_t *rx_buffer, uint32_t length)
{
    rt_kprintf("==rx eth data\n");
    rt_err_t result;

struct pbuf *p=pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
    if(p==NULL)
    {
        rt_kprintf("pbuf_alloc err\n");
        return;
    }
    rt_memcpy((uint8_t *)((uint8_t *)p->payload), rx_buffer, length);
    /* notify to upper layer */
    if(stm32_eth_device.parent.netif->input(p, stm32_eth_device.parent.netif) != ERR_OK )
    {
        rt_kprintf("ethernetif_input: Input error\n");
        pbuf_free(p);
        p = NULL;
    }
#if 0
    result = eth_device_ready(&(stm32_eth_device.parent));
    if (result != RT_EOK)
    {
        rt_kprintf("RxCpltCallback err = %d", result);
    }
    #endif
}

void cy_tx_complete_cb ( ETH_Type *pstcEth, uint8_t u8QueueIndex )
{
    rt_kprintf("[%d]cy_tx_complete_cb\n",__LINE__);
}

void cy_tx_failure_cb ( ETH_Type *pstcEth, uint8_t u8QueueIndex )
{
    //rt_kprintf("[%d]cy_tx_failure_cb\n",__LINE__);
}

static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
    return RT_EOK;
}

static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
    rt_kprintf("emac open\n");
    return RT_EOK;
}

static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
    rt_kprintf("emac close\n");
    return RT_EOK;
}

static rt_ssize_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
    rt_kprintf("emac read\n");
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_ssize_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
    rt_kprintf("emac write\n");
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
    switch (cmd)
    {
    case NIOCTL_GADDR:
        if (args)
        {
            rt_memcpy(args, stm32_eth_device.dev_addr, 6);
        }
        else
        {
            return -RT_ERROR;
        }
        break;
    default :
        break;
    }
    return RT_EOK;
}

static uint8_t data_buffer[CY_ETH_SIZE_MAX_FRAME];

/* ethernet device interface */
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
{
    struct pbuf *q;
    cy_en_ethif_status_t eth_status;
    uint32_t framelen = 0;
    
    if (p->tot_len > (u16_t)CY_ETH_SIZE_MAX_FRAME) 
    {
      return -1;
    }
    for(q = p; q != NULL; q = q->next)
    {
        rt_memcpy(data_buffer + framelen, q->payload, q->len);
        framelen += (uint32_t)q->len;
    }
    //rt_kprintf("ETH1 tx tot_len:%d len:%d\n",p->tot_len, p->len);
    eth_status = Cy_ETHIF_TransmitFrame(ETH1, data_buffer, framelen, CY_ETH_QS0_0, true);
    if(eth_status != CY_ETHIF_SUCCESS)
    {
        rt_kprintf("failed to send outgoing packet:[%d]\n", eth_status);
    }
    return RT_EOK;
}

#if 0
/* receive data*/
uint8_t rx_buffer[2048];
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
    //rt_kprintf("[%d]%s(): ETH1 rx frame\n",__LINE__,__FUNCTION__);
    struct pbuf *p = NULL;
    struct pbuf *q = NULL;
    uint16_t len = 0;
    uint32_t bufferoffset = 0;
    uint32_t payloadoffset = 0;
    uint32_t byteslefttocopy = 0;
    uint32_t i = 0;

if (len > 0)
    {
        /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
        //p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
    }

if (p != NULL)
    {
       // bufferoffset = 0;
       // for (q = p; q != NULL; q = q->next)
        {
          //  byteslefttocopy = q->len;
           // rt_memcpy((uint8_t *)((uint8_t *)q->payload), rx_buffer, len);
        }
    }
    return p;
}
#endif
cy_stc_ephy_t phy_obj;
static void phy_linkchange()
{
    static int link_status = -1;
    rt_kprintf("==== 1s timer\n");
    uint32_t s = Cy_EPHY_GetLinkStatus(&phy_obj);
    if (link_status != s)
    {
        if(s == 0)
        {
            rt_kprintf("====linkchange down\n");
            eth_device_linkchange(&stm32_eth_device.parent, 0);
        }
        if(s == 1)
        {
            rt_kprintf("====linkchange up\n");
            eth_device_linkchange(&stm32_eth_device.parent, 1);
        }
       link_status = s;
    }
}

static void phy_monitor_thread_entry(void *parameter)
{
#if 0
    //eth_device_linkchange(&stm32_eth_device.parent, 0);
//#ifndef PHY_USING_INTERRUPT_MODE
    stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
    if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
    {
        rt_kprintf("Start link change detection timer failed");
    }
//#endif
#endif
#if 1
    static int link_status = -1;
    uint32_t s=0;
    rt_kprintf("====timer\n");
    while(1)
    {
        //rt_kprintf("====check\n");
        s = Cy_EPHY_GetLinkStatus(&phy_obj);
        //rt_kprintf("====link check %d\n",s);
        if (link_status != s)
        {
            if(s == 0)
            {
                rt_kprintf("====linkchange down\n");
                eth_device_linkchange(&stm32_eth_device.parent, 0);
            }
            if(s == 1)
            {
                rt_kprintf("====linkchange up\n");
                eth_device_linkchange(&stm32_eth_device.parent, 1);
            }
            link_status = s;
        }
        rt_thread_mdelay(1000);
    }
    #endif
}

/* Register the EMAC device */
static int rt_hw_stm32_eth_init(void)
{
    rt_err_t state = RT_EOK;

cy_ecm_phy_config_t phy_interface_type;
    phy_interface_type.interface_speed_type = CY_ECM_SPEED_TYPE_RGMII;
    phy_interface_type.phy_speed = CY_ECM_PHY_SPEED_100M;
    phy_interface_type.mode = CY_ECM_DUPLEX_FULL;
    cy_eth_driver_initialization(ETH_INTERFACE_TYPE, &phy_interface_type, &phy_obj);

stm32_eth_device.dev_addr[0] = 0x00;
    stm32_eth_device.dev_addr[1] = 0x03;
    stm32_eth_device.dev_addr[2] = 0x19;
    stm32_eth_device.dev_addr[3] = 0x45;
    stm32_eth_device.dev_addr[4] = 0x00;
    stm32_eth_device.dev_addr[5] = 0x00;

stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
    stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
    stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
    stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
    stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
    stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
    stm32_eth_device.parent.parent.user_data  = RT_NULL;

// stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
    stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;

/* register eth device */
    state = eth_device_init(&(stm32_eth_device.parent), "e0");
    if (RT_EOK == state)
    {
        rt_kprintf("emac device init success\n");
    }
    else
    {
        rt_kprintf("emac device init faild: %d\n", state);
        state = -RT_ERROR;
        goto __exit;
    }

/* start phy monitor */
    rt_thread_t tid;
    tid = rt_thread_create("phy",
                           phy_monitor_thread_entry,
                           RT_NULL,
                           4096,
                           RT_THREAD_PRIORITY_MAX - 2,
                           2);
    if (tid != RT_NULL)
    {
        if(rt_thread_startup(tid)!=RT_EOK)
        {
            rt_kprintf("errrrrrrrrrr 11\n");
        }
    }
    else
    {
        rt_kprintf("errrrrrrrrrr 22\n");
        state = -RT_ERROR;
    }
__exit:
    return state;
}
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);

```
RT-Thread 的 lwIP 移植在原版的基础上，添加了网络设备层以替换原来的驱动层。和原来的驱动层不同的是，对于以太网数据的收发采用了独立的双线程结构，erx 线程和 etx 线程在正常情况下，两者的优先级设置成相同，用户可以根据自身实际要求进行微调以侧重接收或发送。本次配置不配置接收线程，由以太网接收中断把接收到的 pbuf 数据包提交给 lwIP 主任务。

最后编译下载，由于我开始使用的是MDK5.36，发现link up后会卡死，在RTT大佬的帮助下，发现使用KEIL MDK 5.39版本才能编译运行不卡死，暂时未找到深层次原因，尝试换用MDK5.40也会卡死。

![11.png](https://oss-club.rt-thread.org/uploads/20240820/a8e2aa5da0874f9ea677d35152bac16d.png)

使用静态IP，关闭DHCP，ping测试，通过日志和wireshark抓包看，数据能成功发送出去，但是无法进入接收中断，接收不到数据

![22.png](https://oss-club.rt-thread.org/uploads/20240820/4817acc1b90392fa5dfe635779fa1a3a.png)

![微信图片_20240820223935.png](https://oss-club.rt-thread.org/uploads/20240820/b7dd3df9e4f9ba88b29a0d90602abf58.png)

![33.png](https://oss-club.rt-thread.org/uploads/20240820/d069636ff6036958fe7b304c04fab1a9.png.webp)

本次移植实验未能100%成功，只实现了发送，接收无法进中断的问题暂时没有找到深层次原因，关于接收的问题后续深入熟悉英飞凌的SDK慢慢研究了，有进展会及时在论坛分享。

### 附件：

- [drv_eth.h](https://club.rt-thread.org/file_download/d8ad7c02a4e23ac6)
- [drv_eth.c](https://club.rt-thread.org/file_download/e7aa610c10df59b9)

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