stm32 f407ZGTx 外扩外部SRAM IS62WV51216 奇数地址读取为0

发布于 2023-04-10 10:54:26 浏览：378 订阅该版

rt-thread studio 外扩内存使用，初始化成功，偶数位单字节可写可读，奇数位单字节读出来是0
```
msh />sram_test
11111 : 9
22222 : 0
```

```c
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#define BSP_USING_SRAM
#ifdef BSP_USING_SRAM
#include "sdram_port.h"

#define DRV_DEBUG
#define DBG_LVL DBG_LOG
#define LOG_TAG             "drv.sram"
#include <drv_log.h>

#ifdef RT_USING_MEMHEAP_AS_HEAP
struct rt_memheap ex_heap;
#endif

SRAM_HandleTypeDef SRAM_Handler;
int FSMC_SRAM_Init(void)
{
    GPIO_InitTypeDef GPIO_Initure;
    FSMC_NORSRAM_TimingTypeDef FSMC_ReadWriteTim;

__HAL_RCC_FSMC_CLK_ENABLE()
    ;
    __HAL_RCC_GPIOD_CLK_ENABLE()
    ;
    __HAL_RCC_GPIOE_CLK_ENABLE()
    ;
    __HAL_RCC_GPIOF_CLK_ENABLE()
    ;
    __HAL_RCC_GPIOG_CLK_ENABLE()
    ;

SRAM_Handler.Instance = FSMC_NORSRAM_DEVICE;
    SRAM_Handler.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;

SRAM_Handler.Init.NSBank = FSMC_NORSRAM_BANK3;
    SRAM_Handler.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
    SRAM_Handler.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
    SRAM_Handler.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
    SRAM_Handler.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
    SRAM_Handler.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
    SRAM_Handler.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
    SRAM_Handler.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
    SRAM_Handler.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
    SRAM_Handler.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
    SRAM_Handler.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
    SRAM_Handler.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
    SRAM_Handler.Init.ContinuousClock = FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC;

FSMC_ReadWriteTim.AddressSetupTime = 0x00;
    FSMC_ReadWriteTim.AddressHoldTime = 0x00;
    FSMC_ReadWriteTim.DataSetupTime = 0x018;
    FSMC_ReadWriteTim.BusTurnAroundDuration = 0X00;
    FSMC_ReadWriteTim.AccessMode = FSMC_ACCESS_MODE_A;
    HAL_StatusTypeDef status = HAL_SRAM_Init(&SRAM_Handler, &FSMC_ReadWriteTim, &FSMC_ReadWriteTim);
    if (status != HAL_OK)
    {
        rt_kprintf("SRAM init failed!\n");
        return -RT_ERROR;
    }
    else
    {
        rt_kprintf("SRAM init Success\n");
#ifdef RT_USING_MEMHEAP_AS_HEAP
        /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
//        rt_memheap_init(&ex_heap, "sram_ex", (void *) SRAM_BANK_ADDR, SRAM_SIZE);
#endif
    }
    return RT_EOK;
}
INIT_BOARD_EXPORT(FSMC_SRAM_Init);

#define Bank1_SRAM3_ADDR    ((u32)(0x68000000))
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;

void FSMC_SRAM_WriteBuffer(u8* pBuffer, u32 WriteAddr, u32 n)
{
    for (; n != 0; n--)
    {
        *(vu8*) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
        WriteAddr++;
    }
}

void FSMC_SRAM_ReadBuffer(u8* pBuffer, u32 ReadAddr, u32 n)
{
    for (; n != 0; n--)
    {
        *pBuffer++ = *(vu8*) (Bank1_SRAM3_ADDR + ReadAddr);
        ReadAddr++;
    }
}

#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
static int sram_test(void)
{
    u8 temp = 9;
    u8 sval = 0;
    FSMC_SRAM_WriteBuffer(&temp, 100, 1);
    FSMC_SRAM_ReadBuffer(&sval, 100, 1);

rt_kprintf("11111 : %d \r\n", sval);

temp = 10;
    FSMC_SRAM_WriteBuffer(&temp, 101, 1);
    FSMC_SRAM_ReadBuffer(&sval, 101, 1);
    rt_kprintf("22222 : %d \r\n", sval);

return RT_EOK;
}

MSH_CMD_EXPORT(sram_test, sram test);

void* rt_sk_memheap_alloc(rt_size_t size)
{
    void *new_ptr_t = rt_memheap_alloc(&ex_heap, size);
    if (new_ptr_t)
    {
        return new_ptr_t;
    }
    else
    {
        rt_kprintf("rt_sk_memheap_alloc fail, size=%d\n", size);
    }
    return NULL;
}

#endif /* FINSH_USING_MSH */
#endif /* DRV_DEBUG */
#endif /* BSP_USING_SRAM */

```