RT-Thread-stm32f103上使用uffs文件系统RT-Thread问答社区

stm32f103上使用uffs文件系统

发布于 2014-01-23 22:02:00 浏览：2361 订阅该版

在stm32f103zet6，k9f1208上使用UFFS文件系统，移植OK后，系统正常启动，用mkdir建立文件夹成功，ls可查看，可是一重启就出现unclean page found 和新的bad block，如下：```
  | /
- RT -     Thread Operating System
 / |      1.1.1 build Jan 23 2014
 2006 - 2013 Copyright by rt-thread team
rtc is not configured
please configure with set_date and set_time
os  : system memory alloc 320 bytes
flsh: UFFS consume spare data size 14
os  : system memory alloc 22080 bytes
os  : system memory alloc 26800 bytes
os  : system memory alloc 16384 bytes
tree: found bad block 0
tree: DIR 0, FILE 0, DATA 0
uffs initialized!
finsh>>
finsh>>
finsh>>mkdir("/test")
        0, 0x00000000
finsh>>ls()
Directory /:
test                <DIR>                    
        0, 0x00000000
finsh>>reset
        134219225, 0x080005d9
finsh>>reset()

| /
- RT -     Thread Operating System
 / |      1.1.1 build Jan 23 2014
 2006 - 2013 Copyright by rt-thread team
rtc is not configured
please configure with set_date and set_time
os  : system memory alloc 320 bytes
flsh: UFFS consume spare data size 14
os  : system memory alloc 22080 bytes
os  : system memory alloc 26800 bytes
os  : system memory alloc 16384 bytes
tree: found bad block 0
tree: unclean page found, block 2 page 31, mark it.
tree: unclean page found, block 2 page 30, mark it.
tree: unclean page found, block 2 page 29, mark it.
tree: unclean page found, block 2 page 28, mark it.
tree: unclean page found, block 2 page 27, mark it.
tree: unclean page found, block 2 page 26, mark it.
tree: unclean page found, block 2 page 25, mark it.
tree: unclean page found, block 2 page 24, mark it.
tree: unclean page found, block 2 page 23, mark it.
tree: unclean page found, block 2 page 22, mark it.
tree: unclean page found, block 2 page 21, mark it.
tree: unclean page found, block 2 page 20, mark it.
tree: unclean page found, block 2 page 19, mark it.
tree: unclean page found, block 2 page 18, mark it.
tree: unclean page found, block 2 page 17, mark it.
tree: unclean page found, block 2 page 16, mark it.
tree: unclean page found, block 2 page 15, mark it.
tree: unclean page found, block 2 page 14, mark it.
tree: unclean page found, block 2 page 13, mark it.
tree: unclean page found, block 2 page 12, mark it.
tree: unclean page found, block 2 page 11, mark it.
tree: unclean page found, block 2 page 10, mark it.
tree: unclean page found, block 2 page 9, mark it.
tree: unclean page found, block 2 page 8, mark it.
tree: unclean page found, block 2 page 7, mark it.
tree: unclean page found, block 2 page 6, mark it.
tree: unclean page found, block 2 page 5, mark it.
tree: unclean page found, block 2 page 4, mark it.
tree: unclean page found, block 2 page 3, mark it.
tree: unclean page found, block 2 page 2, mark it.
tree: unclean page found, block 2 page 1, mark it.
flsh: Read block 2 page 0 CRC failed
tree: New bad block (3) discovered.
flsh: Mark bad block: 2
tree: DIR 1, FILE 0, DATA 0
uffs initialized!
finsh>>ls()
Directory /:
BAD file: test
        0, 0x00000000
finsh>>```
哪个高手帮忙看下是怎么回事，下面贴出k9f_nand.c和k9f_nand.h代码
k9f_nand.c
```/*
 * File      : k9f2g08u0b.c
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2009 RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://www.rt-thread.org/license/LICENSE
 *
 * Change Logs:
 * Date           Author           Notes
 * 2012-11-24     heyuanjie87      first implementation
 * 2013-03-23     prife            add support for stm32f10x
 */
#include <rtdevice.h>
#include "stm32f10x.h"
#include "k9f_nand.h"
#ifdef RT_USING_DFS_UFFS
#include "uffs/uffs_flash.h"
#endif
#include <string.h>

//#define NAND_DEBUG    rt_kprintf
#define NAND_DEBUG(...)

/* nand bank configure */
#define FSMC_NAND_BANK  FSMC_Bank2_NAND
#define NAND_BANK     ((rt_uint32_t)0x70000000)
#define NAND_LARGE    0 /* k9f1g08 0;  k9f2g08: 1 */

static struct stm32_nand _device;
#if RT_CONFIG_UFFS_ECC_MODE == UFFS_ECC_SOFT
#define ECC_SIZE     0
#elif RT_CONFIG_UFFS_ECC_MODE == UFFS_ECC_HW_AUTO
#define ECC_SIZE     3
#else
#error "please set ECC_SIZE a valid value"
#endif

rt_inline void nand_cmd(rt_uint8_t cmd)
{
    /* write to CMD area */
    *(volatile rt_uint8_t*)(NAND_BANK | CMD_AREA) = cmd;
}

rt_inline void nand_addr(rt_uint8_t addr)
{
    /* write to address area */
    *(volatile rt_uint8_t*)(NAND_BANK | ADDR_AREA) = addr;
}

rt_inline rt_uint8_t nand_read8(void)
{
    /* read 1Byte */
    return (*(volatile rt_uint8_t*)(NAND_BANK | DATA_AREA));
}

rt_inline void nand_write8(rt_uint8_t data)
{
    /* write 1Byte */
    *(volatile rt_uint8_t*)(NAND_BANK | DATA_AREA) = data;
}

rt_inline void nand_waitready(void)
{
    while (GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0);
}

static rt_uint32_t FSMC_NAND_ReadStatus(void)
{
  rt_uint32_t status = NAND_BUSY;

/* Read status operation ------------------------------------ */
  nand_cmd(NAND_CMD_STATUS);

if((nand_read8() & NAND_ERROR) == NAND_ERROR)
  {
    status = NAND_ERROR;
  } 
  else if((nand_read8() & NAND_READY) == NAND_READY)
  {
    status = NAND_READY;
  }
  else
  {
    status = NAND_BUSY; 
  }
  
  return (status);
}

static rt_uint32_t FSMC_NAND_GetStatus(void)
{
  rt_uint32_t timeout = 0x1000000, status = NAND_READY;

status = FSMC_NAND_ReadStatus();

/* Wait for a NAND operation to complete or a TIMEOUT to occur */
  while ((status != NAND_READY) &&( timeout != 0x00))
  {
     status = FSMC_NAND_ReadStatus();
     timeout --;      
  }

if(timeout == 0x00)
  {          
    status =  NAND_TIMEOUT_ERROR;      
  }

/* Return the operation status */
  return (status);      
}

static rt_uint8_t nand_readstatus(void)
{
    nand_cmd(NAND_CMD_STATUS);
    return (nand_read8());
}

static rt_err_t nand_datacorrect(uint32_t generatedEcc, uint32_t readEcc, uint8_t *data)
{
#define ECC_MASK28    0x0FFFFFFF          /* 28 valid ECC parity bits. */
#define ECC_MASK      0x05555555          /* 14 ECC parity bits.       */

rt_uint32_t count, bitNum, byteAddr;
    rt_uint32_t mask;
    rt_uint32_t syndrome;
    rt_uint32_t eccP;                            /* 14 even ECC parity bits. */
    rt_uint32_t eccPn;                           /* 14 odd ECC parity bits.  */

syndrome = (generatedEcc ^ readEcc) & ECC_MASK28;

if (syndrome == 0)
        return (RT_MTD_EOK);                  /* No errors in data. */

eccPn = syndrome & ECC_MASK;              /* Get 14 odd parity bits.  */
    eccP  = (syndrome >> 1) & ECC_MASK;       /* Get 14 even parity bits. */

if ((eccPn ^ eccP) == ECC_MASK)           /* 1-bit correctable error ? */
    {
        bitNum = (eccP & 0x01) |
                 ((eccP >> 1) & 0x02) |
                 ((eccP >> 2) & 0x04);
        NAND_DEBUG("ECC bit %d
",bitNum);
        byteAddr = ((eccP >> 6) & 0x001) |
                   ((eccP >> 7) & 0x002) |
                   ((eccP >> 8) & 0x004) |
                   ((eccP >> 9) & 0x008) |
                   ((eccP >> 10) & 0x010) |
                   ((eccP >> 11) & 0x020) |
                   ((eccP >> 12) & 0x040) |
                   ((eccP >> 13) & 0x080) |
                   ((eccP >> 14) & 0x100) |
                   ((eccP >> 15) & 0x200) |
                   ((eccP >> 16) & 0x400) ;

data[ byteAddr ] ^= 1 << bitNum;

return RT_MTD_EOK;
    }

/* Count number of one's in the syndrome. */
    count = 0;
    mask  = 0x00800000;
    while (mask)
    {
        if (syndrome & mask)
            count++;
        mask >>= 1;
    }

if (count == 1)           /* Error in the ECC itself. */
        return RT_MTD_EECC;

return -RT_MTD_EECC;       /* Unable to correct data. */

#undef ECC_MASK
#undef ECC_MASK24
}

static void gpio_nandflash_init(void)
{
    GPIO_InitTypeDef GPIO_InitStructure;

#if defined(STM32_F4XX)
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);

/* FSMC GPIO config in board.c */

/* NAND_R/B: PG6 */
    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_6;
#else

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
        RCC_APB2Periph_GPIOG | RCC_APB2Periph_AFIO , ENABLE);

/*-- GPIO Configuration ------------------------------------------------------*/
    /* CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
    GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
        GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
        GPIO_Pin_7;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
    GPIO_Init(GPIOD, &GPIO_InitStructure);

/* D4->D7 NAND pin configuration  */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
    GPIO_Init(GPIOE, &GPIO_InitStructure);

/* NWAIT NAND pin configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
    GPIO_Init(GPIOD, &GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
#endif

GPIO_Init(GPIOG, &GPIO_InitStructure);
}

static void fsmc_nandflash_init(void)
{
    FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
    FSMC_NAND_PCCARDTimingInitTypeDef p;

#if defined(STM32_F4XX)
    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
#else
    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
#endif

p.FSMC_SetupTime     = 0x1;
    p.FSMC_WaitSetupTime = 0x3;
    p.FSMC_HoldSetupTime = 0x2;
    p.FSMC_HiZSetupTime  = 0x1;

FSMC_NANDInitStructure.FSMC_Bank = FSMC_NAND_BANK;
    FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
    FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
    FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Disable;/* ??????????ECC???? */
    FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
    FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
    FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
    FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
    FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;

FSMC_NANDInit(&FSMC_NANDInitStructure);

/* FSMC NAND Bank Cmd Test */
    FSMC_NANDCmd(FSMC_NAND_BANK, ENABLE);
}

static struct nand_id nand_table[] =
{
  {{0xEC, 0xF1, 0x80, 0x15}, "K9F1G08U0A"},
  {{0xEC, 0xF1, 0x00, 0x95}, "K9F1G08U0B"},
  {{0xEC, 0xAA, 0x00, 0x15}, "K9F2G08R0A"},
  {{0xEC, 0xDA, 0x10, 0x95}, "K9F1G08U0A"},
  {{0xAD, 0xF1, 0x80, 0x1D}, "HY27UF081G2A"},
	{{0xEC, 0x76, 0x10, 0x95}, "K9F1208U0C"},

{{0x0, 0x0, 0x0, 0x0}, "end"},
};

/* ????OK */
static rt_err_t nandflash_readid(struct rt_mtd_nand_device *mtd)
{
    int i;

nand_cmd(NAND_CMD_READID);
    nand_addr(0);

_device.id[0] = nand_read8();
    _device.id[1] = nand_read8();
    _device.id[2] = nand_read8();
    _device.id[3] = nand_read8();
    NAND_DEBUG("ID[%X,%X]
",_device.id[0], _device.id[1]);
    for (i=0; nand_table->id[0] != 0; i++)
    {
        if (_device.id[0] == nand_table*.id[0] &&
            _device.id[1] == nand_table*.id[1])
            return (RT_EOK);
    }
    NAND_DEBUG("NAND device unsupported!
");

return (RT_ERROR);
}

/* ????OK */
static rt_err_t nandflash_readpage(struct rt_mtd_nand_device* device, rt_off_t page,
                                   rt_uint8_t *data, rt_uint32_t data_len,
                                   rt_uint8_t *spare, rt_uint32_t spare_len)
{
    rt_uint32_t index;
    rt_uint32_t gecc, recc;
    rt_uint8_t tmp[8];
    rt_err_t result;
		rt_uint32_t status = NAND_READY;

NAND_DEBUG("nand read[%d,%d,%d]
",page,data_len,spare_len);
    result = -RT_MTD_EIO;
    rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);

if (data && data_len)
    {
        nand_cmd(NAND_CMD_AREA_A);

nand_addr(0);
        nand_addr(page);
        nand_addr(page >> 8);
        nand_addr(page >> 16);

FSMC_NANDECCCmd(FSMC_NAND_BANK,ENABLE);
        for (index = 0; index < data_len; index ++)
        {
            data[index] = nand_read8();
        }
        gecc = FSMC_GetECC(FSMC_NAND_BANK);
        FSMC_NANDECCCmd(FSMC_NAND_BANK,DISABLE);
				
				status = FSMC_NAND_GetStatus();
				
				if( status == NAND_READY )
						result = RT_MTD_EOK;
				else
				{		
						result = -RT_MTD_EIO;
						goto _exit;
				}
#if RT_CONFIG_UFFS_ECC_MODE == UFFS_ECC_HW_AUTO
        if (data_len == 512)
        {
            nand_cmd(NAND_CMD_AREA_C);
						nand_addr(0);
						nand_addr(page);
						nand_addr(page>>8);
						nand_addr(page>>16);
					
						for (index = 0; index < ECC_SIZE; index ++)
                tmp[index] = nand_read8();
            if (spare && spare_len)
            {
                for (index = 0; index < spare_len-ECC_SIZE; index ++)
                    spare[ECC_SIZE + index] = nand_read8();

spare_len = 0;

memcpy(spare, tmp , ECC_SIZE);
            }

status = FSMC_NAND_GetStatus();
				
						if( status == NAND_READY )
								result = RT_MTD_EOK;
						else
						{		
								result = -RT_MTD_EIO;
								goto _exit;
						}
				
            recc   = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];

NAND_DEBUG("<gecc %X,recc %X>",gecc,recc);
            if (nand_datacorrect(gecc, recc, data) != RT_EOK)
                result = -RT_MTD_EECC;
            else
                result = RT_MTD_EOK;

goto _exit;
        }
#endif
    }

if (spare && spare_len)
    {
				nand_cmd(NAND_CMD_AREA_C);  
        nand_addr(0);
        nand_addr(page);
        nand_addr(page >> 8);
        nand_addr(page >> 16);

for (index = 0; index < spare_len; index ++)
        {
            spare[index] = nand_read8();
        }
				
				status = FSMC_NAND_GetStatus();
				
				if( status == NAND_READY )
						result = RT_MTD_EOK;
				else
						result = -RT_MTD_EIO;
    }
_exit:
    rt_mutex_release(&_device.lock);
    return (result);
}

static rt_err_t nandflash_writepage(struct rt_mtd_nand_device* device, rt_off_t page,
                                    const rt_uint8_t *data, rt_uint32_t data_len,
                                    const rt_uint8_t *spare, rt_uint32_t spare_len)
{
    rt_uint32_t index,status=NAND_READY;
    rt_err_t result;
    rt_uint32_t gecc;

result = -RT_MTD_EIO;
    NAND_DEBUG("nand write[%d,%d]
",page,data_len);
    rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);

if (data && data_len)
    {
				nand_cmd(NAND_CMD_AREA_A);  
				nand_cmd(NAND_CMD_WRITE0);

nand_addr(0);
        nand_addr(page);
        nand_addr(page >> 8);
        nand_addr(page >> 16);

FSMC_NANDECCCmd(FSMC_NAND_BANK,ENABLE);
        for (index = 0; index < data_len; index ++)
        {
            nand_write8(data[index]);
        }
        gecc = FSMC_GetECC(FSMC_NAND_BANK);
        FSMC_NANDECCCmd(FSMC_NAND_BANK,DISABLE);

#if RT_CONFIG_UFFS_ECC_MODE == UFFS_ECC_HW_AUTO
        NAND_DEBUG("<wecc %X>",gecc);
        if (data_len == 512)
        {
            nand_write8((uint8_t)gecc);
            nand_write8((uint8_t)(gecc >> 8));
            nand_write8((uint8_t)(gecc >> 16));
        }
#endif
				nand_cmd(NAND_CMD_WRITE_TRUE1);
				
        status = FSMC_NAND_GetStatus();
				
				if( status != NAND_READY )
				{		
						result = -RT_MTD_EIO;
            goto _exit;
				}
				else
						result = RT_MTD_EOK;
    }

if (spare && spare_len)
    {
				nand_cmd(NAND_CMD_AREA_C);  
				nand_cmd(NAND_CMD_WRITE0);

nand_addr(ECC_SIZE);
        nand_addr(page);
        nand_addr(page >> 8);
        nand_addr(page >> 16);

for (index = 0; index < spare_len-ECC_SIZE; index ++)
        {
            nand_write8(spare[ECC_SIZE+index]);
        }

nand_cmd(NAND_CMD_WRITE_TRUE1);
        
				status = FSMC_NAND_GetStatus();

if( status != NAND_READY )
				{		
						result = -RT_MTD_EIO;
            goto _exit;
				}
				else
						result = RT_MTD_EOK;
    }

_exit:
    rt_mutex_release(&_device.lock);

return (result);
}

// ????OK
rt_err_t nandflash_eraseblock(struct rt_mtd_nand_device* device, rt_uint32_t block)
{
    rt_uint32_t page,status=NAND_READY;
    rt_err_t result;

result = RT_EOK;
    page = block * 32;

rt_mutex_take(&_device.lock, RT_WAITING_FOREVER);

nand_cmd(NAND_CMD_ERASE0);

nand_addr(page);
    nand_addr(page >> 8);
    nand_addr(page >> 16);

nand_cmd(NAND_CMD_ERASE1);

status = FSMC_NAND_GetStatus();
				
		if( status == NAND_READY )
				result = RT_MTD_EOK;
		else
				result = -RT_MTD_EIO;  
	
    rt_mutex_release(&_device.lock);

return (result);
}

static rt_err_t nandflash_checkblock(struct rt_mtd_nand_device* device, rt_uint32_t block)
{
    return (RT_MTD_EOK);
}

static rt_err_t nandflash_markbad(struct rt_mtd_nand_device* device, rt_uint32_t block)
{
    return (RT_MTD_EOK);
}

static struct rt_mtd_nand_driver_ops ops =
{
    nandflash_readid,
    nandflash_readpage,
    nandflash_writepage,
		RT_NULL,
		nandflash_eraseblock,
#if defined(RT_USING_DFS_UFFS) && !defined(RT_UFFS_USE_CHECK_MARK_FUNCITON)
	RT_NULL,
	RT_NULL,
#else
    nandflash_checkblock,
    nandflash_markbad
#endif
};

static struct rt_mtd_nand_device _partition[1];

void rt_hw_mtd_nand_init(void)
{
    gpio_nandflash_init();
    fsmc_nandflash_init();

rt_mutex_init(&_device.lock, "nand", RT_IPC_FLAG_FIFO);

_partition[0].page_size   = 512;
    _partition[0].pages_per_block = 32;
    _partition[0].block_total = 1024;
    _partition[0].oob_size    = 16;
    _partition[0].oob_free    = 12;
    _partition[0].block_start = 0;
    _partition[0].block_end   = 1023;
    _partition[0].ops         = &ops;

rt_mtd_nand_register_device("nand0", &_partition[0]);
}
#include <math.h>
#include <finsh.h>
static uint8_t TxBuffer[NAND_PAGE_SIZE];
static uint8_t RxBuffer[NAND_PAGE_SIZE];
static rt_uint8_t Spare[16];
void ntest(void)
{
    int i,n;
    rt_uint8_t spare[16];

nandflash_readid(0);

/* Erase the Block */
    rt_kprintf("start erase test
");
    for (i = 1; i < 256; i ++)
    {

if (nandflash_eraseblock(RT_NULL, i) != RT_MTD_EOK)
        {
            RT_ASSERT(0);
        }
        else
            rt_kprintf(".");
    }
#if 1
    rt_kprintf("start read write test
");
    /* Clear the buffer */
    for (i = 0; i < 512; i++)
        TxBuffer* = i / 5 -i;
    memset(Spare, 0x33, 16);

for (n = 32; n < 16 * 256; n++)
    {
        memset(RxBuffer, 0, sizeof(RxBuffer));
        memset(spare, 0x0, 16);

if (nandflash_writepage(RT_NULL,n,TxBuffer,512, Spare, 16) != RT_EOK)
        {
            RT_ASSERT(0);
        }
        /* Read back the written data */
        nandflash_readpage(RT_NULL,n,RxBuffer, 512,spare,16);

if( memcmp( (char*)TxBuffer, (char*)RxBuffer, NAND_PAGE_SIZE ) != 0 )
        {
            RT_ASSERT(0);
        }
        if( memcmp( (char*)Spare+4, (char*)spare+4, 12 ) != 0 )
        {
            RT_ASSERT(0);
        }

}
    NAND_DEBUG("Nand Flash is OK 
");
#endif
}

void nread(int page)
{
    int index;

rt_memset(RxBuffer, 0, 512);
    rt_memset(Spare, 0, 16);

if (nandflash_readpage(RT_NULL,page,RxBuffer, 512,Spare,16) != RT_MTD_EOK)
    {
        rt_kprintf("read fail
");
    }
	rt_kprintf("data:
");
    for (index = 0; index < 512; index ++)
    {
        rt_kprintf("%02X,",RxBuffer[index]);
		if ((index+1) % 16 == 0)
			rt_kprintf("
");
    }
	rt_kprintf("
spare:
");
    for (index = 0; index < 16; index ++)
    {
        rt_kprintf("[%02X]", Spare[index]);
		if ((index+1) % 16 == 0)
			rt_kprintf("
");
    }
    rt_kprintf("

");
}

void nreads(int page)
{
    int index;

rt_memset(Spare, 0, 16);

if (nandflash_readpage(RT_NULL,page,RT_NULL, 0,Spare,16) != RT_MTD_EOK)
    {
        rt_kprintf("read fail
");
    }
	rt_kprintf("
spare:
");
    for (index = 0; index < 16; index ++)
    {
        rt_kprintf("[%02X]", Spare[index]);
		if ((index+1) % 16 == 0)
			rt_kprintf("
");
    }
    rt_kprintf("

");
}

void nerase(int block)
{
    nandflash_eraseblock(RT_NULL,block);
}

void nwrite(int page)
{
    memset(TxBuffer, 0xAA, 512);
    memset(Spare, 0x55, 12);
#if 1
    {
        int i;
        for (i = 0; i < 512; i ++)
            TxBuffer* = i/5 - i;
    }
#endif
    nandflash_writepage(RT_NULL,page,TxBuffer,512, Spare, 12);
}

/*void ncopy(int s, int d)
{

if (nandflash_pagecopy(RT_NULL,s,d) != RT_MTD_EOK)
        rt_kprintf("copy fail
");
}
*/

void nand_eraseall()
{
	int index;
	for (index = 0; index < _partition[0].block_total; index ++)
	{
		nandflash_eraseblock(RT_NULL, index);
	}
}
FINSH_FUNCTION_EXPORT(nand_eraseall, erase all of block in the nand flash);
//FINSH_FUNCTION_EXPORT(ncopy, nand copy);
FINSH_FUNCTION_EXPORT(nwrite, nand write);
FINSH_FUNCTION_EXPORT(nerase, nand erase);
FINSH_FUNCTION_EXPORT(nread, nand read);
FINSH_FUNCTION_EXPORT(nreads, nand spare read);
FINSH_FUNCTION_EXPORT(ntest, nand test);
FINSH_FUNCTION_EXPORT_ALIAS(nandflash_readid, nid, read nand id)
[Code=c]
k9f_nand.h
[/Code]/*
 * File      : k9f2g08u0b.h
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2009 RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://www.rt-thread.org/license/LICENSE
 *
 * Change Logs:
 * Date           Author           Notes
 * 2012-11-24     heyuanjie87      first implementation
 */

#ifndef __K9F2G08U0B_H__
#define __K9F2G08U0B_H__

#include <rtdevice.h>

/* nandflash confg */
#define PAGES_PER_BLOCK         32
#define PAGE_DATA_SIZE          512
#define PAGE_OOB_SIZE           16
#define NAND_MARK_SPARE_OFFSET  6

#define CMD_AREA                   (uint32_t)(0x010000)  /* A16 = CLE  high */
#define ADDR_AREA                  (uint32_t)(0x020000)  /* A17 = ALE high */
#define DATA_AREA                  (uint32_t)(0x000000)

/* NAND memory status */
#define NAND_VALID_ADDRESS         ((u32)0x00000100)
#define NAND_INVALID_ADDRESS       ((u32)0x00000200)
#define NAND_TIMEOUT_ERROR         ((u32)0x00000400)
#define NAND_BUSY                  ((u32)0x00000000)
#define NAND_ERROR                 ((u32)0x00000001)
#define NAND_READY                 ((u32)0x00000040)

/* FSMC NAND memory command */
#define	NAND_CMD_AREA_A            ((uint8_t)0x00)
#define	NAND_CMD_AREA_B            ((uint8_t)0x01)
#define NAND_CMD_AREA_C            ((uint8_t)0x50)

#define NAND_CMD_WRITE0            ((u8)0x80)
#define NAND_CMD_WRITE_TRUE1       ((u8)0x10)

#define NAND_CMD_ERASE0             ((uint8_t)0x60)
#define NAND_CMD_ERASE1             ((uint8_t)0xD0)

#define NAND_CMD_READID             ((uint8_t)0x90)
#define NAND_CMD_STATUS             ((uint8_t)0x70)
#define NAND_CMD_RESET              ((uint8_t)0xFF)

#define NAND_PAGE_SIZE    (512)

struct stm32_nand
{
    rt_uint8_t id[5];
    struct rt_mutex lock;
    struct rt_completion comp;
};

struct nand_id
{
    rt_uint8_t id[4];
    const char * name;
};

void rt_hw_mtd_nand_init(void);

#endif /* __K9F2G08U0B_H__ */
```