求助，RT-Thread 1.2.1, STM32f407, DP83848 ping不通，能收不能发数据帧

发布于 2016-04-07 01:09:57 浏览：5457 订阅该版

是这样的：我正在做一个题目是：基于STM32的嵌入式网关设计。我选择了在RT-Thread 1.2.1系统，STM32F407芯片和DP83848 PHY芯片（SMT32通过RMII模式与DP83848连接）。
现在我正在进行移植LwIP 1.4.1，参考，然后便写了底层驱动程序。但遇见问题是怎么设置都无法ping通（ping 显示 Request time out）。我已有裸机能跑，能ping通的程序，但现在想在RT—Thread 上跑就出了问题。
我也进行了调试发现，模块能接受主机发的帧，能进入中断，也能跑到 stm32_eth_tx()函数进行发送帧，TxBuffer 的数据也对（前6字节是主机的MAC 地址，继续是板子的MAC地址，后面是乱七八糟东西）。DMA和MAC 的寄存器也跟裸机能跑的程序进行对比，完全没问题。但就是不知道。怎么发不出去。
下面是我调试的时候，MAC，ETH_DMA, PHY,以及Tx，RxBuffer 的数据。自己觉得都没有问题。
现在我很迷茫，不知道从哪儿入手找错误地方。很希望个位高人能指点我一下。
``` | /
- RT - Thread Operating System
/ |  1.2.1 build Apr 7 2016
2006 - 2013 Copyright by rt-thread team
lwIP-1.4.1 initialized!
TCP/IP initialized!

TCPServer Waiting for client on port 5000...
finsh>>phy_search()
PHY_BCR = 0x1000 //Auto-Negotiation Enabled
PHY_BSR = 0x786D //Auto-Negotiation process complete, Valid link established, 
PHY_SR = 0x4715 //Full duplex mode, 100 Mb/s mode
PHY_CR = 0x8021 //PHY Address: 0x01, LED mode 1
PHY_RBR = 0x0021 //工作模式为RMII
0, 0x00000000
finsh>>eth_check()
MAC register:
MACCR = 0xce0c 
MACMIIAR = 0x dcc
MACFCR = 0x 80
MACSR = 0x 0
DMA register:
DMABMR = 0x2c16080
DMAOMR = 0x2202006
DMASR = 0x660404
DMAIER = 0x10041
0, 0x00000000
finsh>>eth_tx_status()
Descriptor status:
Address of DMATxDecsToSet = 0x20000420
Status = 0x40100000
ControlBufferSize = 0x 0
Buffer1Addr = 0x20002204
Buffer2NextDescAddr = 0x20000400
Transmit DMA register status:
DMACHTBAR = 0x20002204 
DMACHTDR = 0x20000420
DMATDLAR = 0x20000400
DMASR = 0x660404
DMAIER = 0x10041
0, 0x00000000```

非常感谢！

7 个回答

LacDaSayBia 2016-04-07

这家伙很懒，什么也没写！

```

#include <rtthread.h>
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "stm32f4x7_eth.h"
#include "stm32f4x7_eth_bsp.h"
#include "lwip/tcp.h"
#include "lwip/udp.h"
#include "string.h"

/*********************************************************************************/
 
/* Private define ------------------------------------------------------------*/
#define   	DP83848_PHY_ADDRESS     0x01    // DP83848 PHY???????·.
//#define CHECKSUM_BY_HARDWARE 
/* Ethernet Rx & Tx DMA Descriptors */
extern ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];

/* Ethernet Receive buffers  */
extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];

/* Ethernet Transmit buffers */
extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];

/* Global pointers to track current transmit and receive descriptors */
extern ETH_DMADESCTypeDef  *DMATxDescToSet;
extern ETH_DMADESCTypeDef  *DMARxDescToGet;

/* Global pointer for last received frame infos */
extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;

#define MAX_ADDR_LEN 6

struct rt_stm32_eth
{
    /* inherit from ethernet device */
    struct eth_device parent;

/* interface address info. */
    rt_uint8_t  dev_addr[MAX_ADDR_LEN];            /* hw address    */
};
static struct rt_stm32_eth stm32_eth_device;

static void ETH_MACDMA_Config(void);

/****************************************************************************
* ??    ??: void ETH_BSP_Config(void)
* ??    ????ETH??????
* ?????????? 
* ·???????????
* ??    ?÷??       
****************************************************************************/	
void ETH_BSP_Config(void)
{
  RCC_ClocksTypeDef RCC_Clocks;   	// Configure the GPIO ports for ethernet pins

ETH_GPIO_Config();
  
  ETH_NVIC_Config();      // Config NVIC for Ethernet

ETH_MACDMA_Config();    // Configure the Ethernet MAC/DMA

RCC_GetClocksFreq(&RCC_Clocks);  // SystTick configuration: an interrupt every 10ms   
  SysTick_Config(RCC_Clocks.SYSCLK_Frequency / 100);

/* Update the SysTick IRQ priority should be higher than the Ethernet IRQ */
  /* The Localtime should be updated during the Ethernet packets processing */
  NVIC_SetPriority (SysTick_IRQn, 1);  
}

/****************************************************************************
* ??    ??: static void ETH_MACDMA_Config(void)
* ??    ????ETH DMA??????
* ?????????? 
* ·???????????
* ??    ?÷??       
****************************************************************************/
static void ETH_MACDMA_Config(void)
{
  ETH_InitTypeDef ETH_InitStructure;

/* Enable ETHERNET clock  */
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
                         RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);

ETH_DeInit(); /* Reset ETHERNET on AHB Bus */

ETH_SoftwareReset();   /* Software reset */

while (ETH_GetSoftwareResetStatus() == SET);  /* Wait for software reset */
	
  /* ETHERNET Configuration --------------------------------------------------*/
  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
  ETH_StructInit(Ð_InitStructure);

/* Fill ETH_InitStructure parametrs */
  /*------------------------   MAC   -----------------------------------*/
  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
//	ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; 
//  ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
//  ETH_InitStructure.ETH_Mode = ETH_Mode_HalfDuplex ;

ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
#ifdef CHECKSUM_BY_HARDWARE
  ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif

/*------------------------   DMA   -----------------------------------*/  
  
  /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 
  the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 
  if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
  ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; 
  ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         
  ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
 
  ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
  ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   
  ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
  ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      
  ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                
  ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          
  ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
  ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;

/* Configure Ethernet */
  ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS);

/* Enable the Ethernet Rx Interrupt */
  ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE);
}

/****************************************************************************
* ??    ??: void ETH_GPIO_Config(void)
* ??    ????ETH GPIO??????
* ?????????? 
* ·???????????
* ??    ?÷??????DP83848??IO??????       
****************************************************************************/
void ETH_GPIO_Config(void)
{
  GPIO_InitTypeDef GPIO_InitStructure;
    volatile int i;
  /* Enable GPIOs clocks */
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOG |
                         RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD, ENABLE);
    
  /* Enable SYSCFG clock */
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
 
	SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); //MAC??PHY????????RMII????

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;  
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
  GPIO_Init(GPIOA, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
  GPIO_Init(GPIOC, &GPIO_InitStructure);
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
                                
  /* Configure PG11, PG14 and PG13 */
  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
  GPIO_Init(GPIOG, &GPIO_InitStructure);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
}

/****************************************************************************
* ??    ??: void ETH_NVIC_Config(void)
* ??    ????ETH ??????????
* ?????????? 
* ·???????????
* ??    ?÷??????DP83848??IO??????       
****************************************************************************/
void ETH_NVIC_Config(void)
{
  NVIC_InitTypeDef   NVIC_InitStructure;

/* 2 bit for pre-emption priority, 2 bits for subpriority */
  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); 
  
  /* Enable the Ethernet global Interrupt */
  NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);    
}

/* interrupt service routine */
void ETH_IRQHandler(void)
{
	rt_uint32_t status, ier;
	rt_uint32_t nis_clear;
	
	rt_interrupt_enter(); 
  status = ETH->DMASR;
	ier = ETH->DMAIER;
	if(status & ETH_DMA_IT_MMC)
    {
        rt_kprintf("ETH_DMA_IT_MMC
");
        ETH_DMAClearITPendingBit(ETH_DMA_IT_MMC);
    }

if(status & ETH_DMA_IT_NIS)
   {
			nis_clear = ETH_DMA_IT_NIS;
        /* [0]:Transmit Interrupt. */
		 if((status & ier) & ETH_DMA_IT_T) /* packet transmission */
			 {
				 rt_kprintf("ETH_DMA_IT_T
");
				 nis_clear |= ETH_DMA_IT_T;
       }
			 if((status & ier) & ETH_DMA_IT_R) /* packet reception */
       {
				//	rt_kprintf("ETH_DMA_IT_R
");
           /* a frame has been received */
          eth_device_ready(&(stm32_eth_device.parent)); 
					nis_clear |= ETH_DMA_IT_R;				 
        }
    }
	/* Clear the Eth DMA Rx IT pending bits */
	ETH_DMAClearITPendingBit(nis_clear);
	rt_interrupt_leave();
}

/* RT-Thread Device Interface */
/* initialize the interface */
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
	int i;
    /* MAC address configuration */
	ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);

/* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
  
#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
  for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
#endif

/* Note: TCP, UDP, ICMP checksum checking for received frame are enabled in DMA config */

/* Enable MAC and DMA transmission and reception */
  ETH_Start();

return RT_EOK;
}

static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
    return RT_EOK;
}

static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
    return RT_EOK;
}

static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer,
                                   rt_size_t size)
{
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos,
                                     const void* buffer, rt_size_t size)
{
    rt_set_errno(-RT_ENOSYS);
    return 0;
}

static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd,
                                     void *args)
{
    switch(cmd)
    {
        case NIOCTL_GADDR:
            /* get mac address */
            if(args)
							memcpy(args, stm32_eth_device.dev_addr, 6);
            else 
							return -RT_ERROR;
            break;

default :
            break;
    }

return RT_EOK;
}

/* reception packet. */
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
    struct pbuf *p, *q;
    u16_t len;
    uint32_t l = 0, i = 0;
    FrameTypeDef frame;
    u8 *buffer;
    __IO ETH_DMADESCTypeDef *DMARxNextDesc;
		
		int index = 0; //for test

p = RT_NULL;

/* Get received frame */
    frame = ETH_Get_Received_Frame_interrupt();

if( frame.length > 0 )
    {
        /* check that frame has no error */
        if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
        {
            //rt_kprintf("Get a frame  buf = 0x%X, len= %d
",frame.buffer, frame.length);
            /* Obtain the size of the packet and put it into the "len" variable. */
            len = frame.length;
            buffer = (u8 *)frame.buffer;

/* We allocate a pbuf chain of pbufs from the pool. */
            p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);

/* Copy received frame from ethernet driver buffer to stack buffer */
            if (p != NULL)
            {
                for (q = p; q != NULL; q = q->next)
                {
                    rt_memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
                    l = l + q->len;
                }
            }
        }

/* Release descriptors to DMA */
        /* Check if received frame with multiple DMA buffer segments */
        if (DMA_RX_FRAME_infos->Seg_Count > 1)
        {
            DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
        }
        else
        {
            DMARxNextDesc = frame.descriptor;
        }

/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
        for (i = 0; i < DMA_RX_FRAME_infos->Seg_Count; i++)
        {
            DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
            DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
        }

/* Clear Segment_Count */
        DMA_RX_FRAME_infos->Seg_Count = 0;

/* When Rx Buffer unavailable flag is set: clear it and resume reception */
        if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
        {
            /* Clear RBUS ETHERNET DMA flag */
            ETH->DMASR = ETH_DMASR_RBUS;

/* Resume DMA reception */
            ETH->DMARPDR = 0;
        }
    }	
    return p;
}

rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
{
	struct pbuf *q;
	rt_uint32_t offset;
	
	offset = 0;
	for(q = p; q != NULL; q = q->next)
	{
		uint8_t *to;
		to = (uint8_t*)((DMATxDescToSet->Buffer1Addr) + offset);
		memcpy(to, q->payload, q->len);
		offset += q->len;
	}
	ETH->DMAOMR |= ETH_DMAOMR_FTF;
	DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1);
	
	DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
	
	DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
	
	if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
	{
		ETH->DMASR = ETH_DMASR_TBUS;
		ETH->DMATPDR = 0;
	}
	
	DMATxDescToSet = (ETH_DMADESCTypeDef*)(DMATxDescToSet->Buffer2NextDescAddr);
	DMATxDescToSet->Status |= ETH_DMATxDesc_IC;
	return RT_EOK;
}
/*{
  struct pbuf *q;
  uint32_t framelength = 0;
  u8 *buffer =  (u8 *)(DMATxDescToSet->Buffer1Addr);
	int index = 0, i = 0;
  
  // copy frame from pbufs to driver buffers 
  for(q = p; q != NULL; q = q->next) 
  {
    memcpy((u8_t*)&buffer[framelength], q->payload, q->len);
	framelength = framelength + q->len;
  }
  
  //Note: padding and CRC for transmitted frame 
  //   are automatically inserted by DMA

// Prepare transmit descriptors to give to DMA
	ETH->DMAOMR |= ETH_DMAOMR_FTF;
  ETH_Prepare_Transmit_Descriptors(framelength);
  return ERR_OK;
}
*/
rt_err_t rt_hw_stm32_eth_init(void)
{
		uint8_t mac[6]="THANH!";
		int i;
	
		ETH_BSP_Config();

stm32_eth_device.dev_addr[0] = 0x00;
		stm32_eth_device.dev_addr[1] = 0x00;
    stm32_eth_device.dev_addr[2] = 0x00;
		stm32_eth_device.dev_addr[3] = 0x00;
    stm32_eth_device.dev_addr[4] = 0x00;
    stm32_eth_device.dev_addr[5] = 0x01;

stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
    stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
    stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
    stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
    stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
    stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
    stm32_eth_device.parent.parent.user_data  = RT_NULL;

stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
    stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;

/* register eth device */
    eth_device_init(&(stm32_eth_device.parent), "e0");
    
    return RT_EOK;
}
#ifdef RT_USING_FINSH
#include <finsh.h>
static void phy_search(int argc, char** argv)
{
    int value;
		value = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR); 
		rt_kprintf("PHY_BCR = 0x%04X
", value);
    value = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
    rt_kprintf("PHY_BSR = 0x%04X
", value);
		value = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
    rt_kprintf("PHY_SR = 0x%04X
", value);
		value = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, 0x19); 
		rt_kprintf("PHY_CR = 0x%04X
", value);
		value = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, 0x17); 
		rt_kprintf("PHY_RBR = 0x%04X
", value);
		
}

FINSH_FUNCTION_EXPORT(phy_search, search phy use MDIO);

static void eth_check(int argc, char** argv)
{
    int value;
		rt_kprintf("MAC register:
");
		value = ETH->MACCR;
		rt_kprintf("MACCR = 0x%4x
", value);
		value = ETH->MACMIIAR;
		rt_kprintf("MACMIIAR = 0x%4x
", value);
		value = ETH->MACFCR;
		rt_kprintf("MACFCR = 0x%4x
", value);
		value = ETH->MACSR;
		rt_kprintf("MACSR = 0x%4x
", value);
	
		rt_kprintf("DMA register:
");
		value = ETH->DMABMR;
		rt_kprintf("DMABMR = 0x%4x
", value);
		value = ETH->DMAOMR;
		rt_kprintf("DMAOMR = 0x%4x
", value);
		value = ETH->DMASR;
		rt_kprintf("DMASR = 0x%4x
", value);
		value = ETH->DMAIER;
		rt_kprintf("DMAIER = 0x%4x
", value);
}

FINSH_FUNCTION_EXPORT(eth_check, Check ethernet module);

static void eth_tx_status(int argc, char** argv)
{
	uint32_t status;
	
	rt_kprintf("Descriptor status:
");
	
	rt_kprintf("Address of DMATxDecsToSet =  0x%x
", DMATxDescToSet);
	status = DMATxDescToSet->Status;
	rt_kprintf("Status = 0x%4x
", status);
	status = DMATxDescToSet->ControlBufferSize;
	rt_kprintf("ControlBufferSize = 0x%4x
", status);
	status = DMATxDescToSet->Buffer1Addr;
	rt_kprintf("Buffer1Addr = 0x%4x
", status);
	status = DMATxDescToSet->Buffer2NextDescAddr;
	rt_kprintf("Buffer2NextDescAddr = 0x%4x
",status);
	
	rt_kprintf("Transmit DMA register status:
");
	
	status = ETH->DMACHTBAR;
	rt_kprintf("DMACHTBAR = 0x%4x
", status);
	status = ETH->DMACHTDR;
	rt_kprintf("DMACHTDR = 0x%4x
", status);
	status = ETH->DMATDLAR;
	rt_kprintf("DMATDLAR = 0x%4x
", status);
	
	status = ETH->DMASR;
	rt_kprintf("DMASR = 0x%4x
", status);
	status = ETH->DMAIER;
	rt_kprintf("DMAIER = 0x%4x
", status);
}

FINSH_FUNCTION_EXPORT(eth_tx_status, Check transmit status);

static void check_tx_rx(int argc, char** argv)
{
	uint32_t i;
	
	rt_kprintf("Tx Buffer:
");
	for(i = 0; i < 150 ; i++)
	{
		rt_kprintf("0x%2x ", Tx_Buff[1][i]);
	}
	rt_kprintf("
");
	rt_kprintf("Rx Buffer:
");
	for(i = 0; i < 150 ; i++)
	{
		rt_kprintf("0x%2x ", Rx_Buff[1][i]);
	}
}

FINSH_FUNCTION_EXPORT(check_tx_rx, Check TX RX buffer status);

#endif

#ifdef RT_USING_FINSH
#include <finsh.h>

#endif

```

LacDaSayBia 2016-04-07

这家伙很懒，什么也没写！

LacDaSayBia 2016-04-07

这家伙很懒，什么也没写！

ping 的时候再 TxBuff 和RxBuf　留下的数据。我的主机的MAC: BC-AE-C5-D1-C8-25 , PHY_DP83848的MAC:0,0,0,0,0,1

```
check_tx_rx()
Tx Buffer:
0xbc 0xae 0xc5 0xd1 0xc8 0x25 0x 0 0x 0 0x 0 0x 0 0x 0 0x 1 0x 8 0x 0 0x45 0x 0 0x 0 0x3c 0x29 0x2d 0x 0 0x 0 0xff 0x 1 0x 0 0x 0 0xc0 0xa8 0x 1 0x44 0xc0 0xa8 0x 1 0x b 0x 0 0x 0 0x54 0x35 0x 0 0x 1 0x 1 0x26 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 
Rx Buffer:
0x 0 0x 0 0x 0 0x 0 0x 0 0x 1 0xbc 0xae 0xc5 0xd1 0xc8 0x25 0x 8 0x 0 0x45 0x 0 0x 0 0x3c 0x29 0x2d 0x 0 0x 0 0x80 0x 1 0x8d 0xf4 0xc0 0xa8 0x 1 0x b 0xc0 0xa8 0x 1 0x44 0x 8 0x 0 0x4c 0x35 0x 0 0x 1 0x 1 0x26 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x3e 0x47 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x49 0xb2 0x75 0x76 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0 0x 0
```