RT-Thread-标准版rt_thread中用STM32H563串口空闲中断+DMA接收数据RT-Thread问答社区

标准版rt_thread中用STM32H563串口空闲中断+DMA接收数据

发布于 2024-11-01 17:45:43 浏览：136 订阅该版

DMA缓冲区，每次只能正确接收4的整数倍字节，并且DMA接收缓冲区大小只能设置在63个字节及以下，求救如何解决问题（裸机跑过没有任何问题））
DMA配置代码

```c
struct rt_serial_rx_fifo *rx_fifo;
    DMA_HandleTypeDef *DMA_Handle;
    struct dma_config *dma_config;
    struct stm32_uart *uart;

RT_ASSERT(serial != RT_NULL);
    RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
    uart = rt_container_of(serial, struct stm32_uart, serial);

if (RT_DEVICE_FLAG_DMA_RX == flag)
    {
        DMA_Handle = &uart->dma_rx.handle;
        dma_config = uart->config->dma_rx;
    }
    else /* RT_DEVICE_FLAG_DMA_TX == flag */
    {
        DMA_Handle = &uart->dma_tx.handle;
        dma_config = uart->config->dma_tx;
    }
    LOG_D("%s dma config start", uart->config->name);

{
        rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
    || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
        /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
        SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
        tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
    || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H5)
        /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
        SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
        tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32MP1)
        /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
        SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
        tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
#endif

#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
        /* enable DMAMUX clock for L4+ and G4 */
        __HAL_RCC_DMAMUX1_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
        __HAL_RCC_DMAMUX_CLK_ENABLE();
#endif

UNUSED(tmpreg);   /* To avoid compiler warnings */
    }

if (RT_DEVICE_FLAG_DMA_RX == flag)
    {
        __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
    }
    else if (RT_DEVICE_FLAG_DMA_TX == flag)
    {
        __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
    }

#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
    DMA_Handle->Instance                 = dma_config->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
    DMA_Handle->Instance                 = dma_config->Instance;
    DMA_Handle->Init.Channel             = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
    DMA_Handle->Instance                 = dma_config->Instance;
    DMA_Handle->Init.Request             = dma_config->request;
#endif
    //DMA_Handle->Instance                 = dma_config->Instance;
    DMA_Handle->Init.Request             = dma_config->request;
		DMA_Handle->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
		DMA_Handle->Init.SrcInc = DMA_SINC_FIXED; 
		DMA_Handle->Init.DestInc = DMA_DINC_INCREMENTED;
		DMA_Handle->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE; 
		DMA_Handle->Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
		DMA_Handle->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;   
//		DMA_Handle->Init.SrcBurstLength=1;
//		DMA_Handle->Init.DestDataWidth=1;
		DMA_Handle->Init.TransferAllocatedPort=DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
		
    if (RT_DEVICE_FLAG_DMA_RX == flag)
    {
        DMA_Handle->Init.Direction           = DMA_PERIPH_TO_MEMORY;
        DMA_Handle->Init.Mode                = DMA_NORMAL;
    }
    else if (RT_DEVICE_FLAG_DMA_TX == flag)
    {
        DMA_Handle->Init.Direction           = DMA_MEMORY_TO_PERIPH;
        DMA_Handle->Init.Mode                = DMA_NORMAL;
    }

DMA_Handle->Init.Priority            = DMA_HIGH_PRIORITY;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
    DMA_Handle->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
#endif
//    if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
//    {
//        RT_ASSERT(0);
//    }

if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
    {
        RT_ASSERT(0);
    }
		//__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
		HAL_DMA_ConfigChannelAttributes(DMA_Handle, DMA_CHANNEL_NPRIV);
    /* enable interrupt */
    if (flag == RT_DEVICE_FLAG_DMA_RX)
    {
        rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
        /* Start DMA transfer */
        if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
        {
            /* Transfer error in reception process */
            RT_ASSERT(0);
        }
	
        CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
        __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
				
			//	__HAL_DMA_ENABLE_IT(DMA_Handle, DMA_IT_TC);
    }

/* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
//    HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
//    HAL_NVIC_EnableIRQ(dma_config->dma_irq);

HAL_NVIC_SetPriority(uart->config->irq_type, 3, 3);
    HAL_NVIC_EnableIRQ(uart->config->irq_type);
```

中断处理代码：
```c
	struct rt_serial_rx_fifo *rx_fifo;
				rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
				uint8_t ucTmp=0;
				ucTmp = uart->handle.Instance->ISR;
				ucTmp= uart->handle.Instance->RDR;
				
				HAL_UART_DMAStop(&(uart->handle));
				rx_fifo->get_index=0;
				rx_fifo->put_index=0;
        dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
				
				HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz);
				//rt_memset(rx_fifo->buffer,0, serial->config.bufsz);
				//CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
        __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
```