LPC2478外挂SDRAM还需要设置什么

发布于 2011-12-13 13:14:44 浏览：6841 订阅该版

11 个回答

bernard 2011-12-13

这家伙很懒，什么也没写！

bernard 2011-12-13

这家伙很懒，什么也没写！

江南孤舟 2011-12-13

这家伙很懒，什么也没写！

江南孤舟 2011-12-13

这家伙很懒，什么也没写！

江南孤舟 2011-12-13

这家伙很懒，什么也没写！

aozima 2011-12-13

调网络不抓包，调I2C等时序不上逻辑分析仪，就像电工不用万用表！多用整理的好的文字，比截图更省流量，还能在整理过程中思考。

江南孤舟 2011-12-13

这家伙很懒，什么也没写！

bernard 2011-12-13

这家伙很懒，什么也没写！

江南孤舟 2011-12-13

这家伙很懒，什么也没写！

江南孤舟 2011-12-14

这家伙很懒，什么也没写！

>如何开启SDRAM与RT-Thread没什么关系。
>
>可以先不要在MDK里面勾上SDRAM部分，也不要在RT-Thread把SDRAM把配置为Heap.
>先独立对SDRAM做一下测试，
>
>然后把SDRAM配置成heap做rt_malloc用。
>
>mem_test可以使用：
>[https://rt-thread.googlecode.com/svn/trunk/examples/test/mem_test.c](https://rt-thread.googlecode.com/svn/tr ... mem_test.c)

---

昨天测试了下，开始我的PCONP没有打开。现在测试通过，但在MDK里面勾上SDRAM部分，还是不对，你所说的“在RT-Thread把SDRAM把配置为Heap”是怎么设置的，是启动代码的内容吗？以下是我的测试代码，已通过.

```
/*
 * File      : app.c
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Development Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
 * 2008-12-11     xuxinming    the first version
 */

#include <LPC24xx.h>
#include <rtthread.h>
#define INT32U unsigned long

/**
 * @addtogroup LPC2478
 */
/*@{*/

char thread1_stack[512];
char thread2_stack[512];

struct rt_thread thread1;
struct rt_thread thread2;

void thread1_entry(void* parameter)
{
	int i;

while (1)
	{
		for (i = 0; i < 10; i ++)
		{
			rt_kprintf("%d
", i);
			rt_thread_delay(100);
		}
	}
}

void  sysDelayNS(INT32U  uiDly)
{  
    INT32U  i;
    for(; uiDly > 0; uiDly--){
        for(i = 0; i < 5000; i++);
    }
}void  SDRAMInit( void )
{  
    volatile INT32U i, dummy ;

LCD_CTRL = 0x00;
	sysDelayNS(10);

PCONP |= 1 << 11;
    
    /* 
    * 使能SDRAM总线连接 
    */
#if 1
    PINSEL4   |= 0x50000000;//SRAM(CS2,CS3)
    PINSEL5   |= 0x05010555;//SDRAM(CS0,CS1)
    PINSEL6   |= 0x55555555;//D0~D15
    PINSEL8   |= 0x15555555;//A0~A15
    PINSEL9   |= 0x50550000;//A16~A23 , /OE , /WE , BLS0 , BLS1 , /CS0 , /CS1;
    EMC_CTRL = 0x00000001;		                                    /* Disable Address mirror       */
#else
	//原程序
    PINSEL4   |= 0x50000000;//SRAM(CS2,CS3)
    PINSEL5   |= 0x05050555;//SDRAM(CS0,CS1)
    PINSEL6   |= 0x55555555;//D0~D15
    PINSEL8   |= 0x55555555;//A0~A15
    PINSEL9   |= 0x50555555;//A16~A23 , /OE , /WE , BLS0 , BLS1 , /CS0 , /CS1;
    EMC_CTRL = 0x00000001;		                                    /* Disable Address mirror       */

#endif
    /* 
     * 设置SDRAM访问时序. 
     */
    EMC_DYN_RP        = 1;
    EMC_DYN_RAS       = 2;
    EMC_DYN_SREX      = 1;
    EMC_DYN_APR       = 1;
    EMC_DYN_DAL       = 5;
    EMC_DYN_WR        = 2;
    EMC_DYN_RC        = 3;
    EMC_DYN_RFC       = 3;
    EMC_DYN_XSR       = 5;
    EMC_DYN_RRD       = 1;
    EMC_DYN_MRD       = 2;

EMC_DYN_RD_CFG = 1;                                           /*  Command delayed strategy    */

/*
     * Default setting,
     * RAS latency 3 CCLKs,
     * CAS latenty 3 CCLKs.
     */
    EMC_DYN_RASCAS0   = 0x00000303;

/*
     * 64MB, 1Mx16,
     * 4 banks, row=12,
     * column=8
     */
    EMC_DYN_CFG0   = 0x00000280;
    for (i = 0; i < 0x80; i++) {
    }

/*
     * Mem clock enable,
     * CLKOUT runs, send command:
     * NOP
     */
    EMC_DYN_CTRL   = 0x00000183;
    for (i = 0; i < 0x80; i++) {
    }

/*
     * Send command:
     * PRECHARGE-ALL,
     * shortest possible refresh period
     */
    EMC_DYN_CTRL   = 0x00000103;
    for (i = 0; i < 0x80; i++) {
    }

/*
     * set 32 CCLKs
     * between SDRAM refresh
     * cycles
     */
    EMC_DYN_RFSH   = 0x00000004;
    for (i = 0; i < 0x80; i++) {                                        /*  wait 128 AHB clock cycles   */
    }

/*
     * set 45 x 16CCLKs=720CCLK=15us
     * between SDRAM refresh
     * cycles
     */
    EMC_DYN_RFSH   = 45;

/*
     * To set mode register in SDRAM,
     * enter mode by issue  MODE command, after finishing,
     * bailout and back to NORMAL mode.
     * Mem clock enable, CLKOUT runs, send command: MODE
     */
    EMC_DYN_CTRL   = 0x00000083;
    dummy               = *((volatile int *)(0xA0019800));
    EMC_DYN_CTRL   = 0x00000000;                                   /*  Send command: NORMAL        */
    EMC_DYN_CFG0   = 0x00080280;                                   /*  Enable buffer               */
    for (i = 0; i < 0x80; i++) {
    }

}

#define TEST_ADDR 	0xA011FF00		/* 测试起始地址				*/
#define SIZE		100				/* 测试100个SDRAM空间		*/

#define BEEP		(1<<0)
#define BeepOFF()  	FIO0SET |= BEEP
#define BeepON() 	FIO0CLR |= BEEP
void thread2_entry(void* parameter)
{
	volatile int count = 0;
	unsigned long i;
	rt_uint8_t * p_uint8_t = (rt_uint8_t *)TEST_ADDR;

PINSEL0 &= ~0x00000003;
	SCS |= 0x01;
	FIO0DIR |= BEEP;
	BeepOFF();

// 初始化SDRAM接口
	SDRAMInit();

// 测试SDRAM连接是否正常
    p_uint8_t = (rt_uint8_t *)TEST_ADDR;
	for (i=0;i < SIZE;i++)
		*p_uint8_t++ = (rt_uint8_t)i;

p_uint8_t = (rt_uint8_t *)TEST_ADDR;
    for(i=0; i<SIZE; i++)
    {
        if( *p_uint8_t != (rt_uint8_t)i )
        {
            while(1);
        }
        p_uint8_t++;
    }
// end

while (1)
	{
		//rt_kprintf("Thread2 count:%d
", count++);
		//rt_thread_delay(50);

BeepON();	
		rt_thread_delay(50);
		BeepOFF();	
		rt_thread_delay(50);
	}
}

int rt_application_init()
{
//	rt_thread_init(&thread1,
//		"thread1",
//		thread1_entry, RT_NULL,
//		&thread1_stack[0], sizeof(thread1_stack),
//		20, 10);

rt_thread_init(&thread2,
		"thread2",
		thread2_entry, RT_NULL,
		&thread2_stack[0], sizeof(thread2_stack),
		25, 8);

//	rt_thread_startup(&thread1);
	rt_thread_startup(&thread2);

return 0;
}

/*@}*/
```