用HPM6750evk搭配YT8512H的phy芯片，配置好时钟和IO，初始化的时候会卡在SWR复位的地方，一直不复位，有遇见这种情况的么？

发布于 2024-12-20 19:57:20 浏览：351 订阅该版

卡住的代码如下：

```c
static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr, uint8_t pbl)
{
    /* generate software reset */
    ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_SWR_MASK;

/* wait for the completion of reset process */
    rt_kprintf("start ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)=%d\r\n",ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE));
    while (ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)) {
//    	rt_kprintf("start ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)=%d\r\n",ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE));
    }
    rt_kprintf("end ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)=%d\r\n",ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE));
    /* initialize bus mode register */
    ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_AAL_MASK;

ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_FB_MASK;

/* enable pblx8 mode */
    ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBLX8_MASK;

/* set programmable burst length */
    ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_PBL_MASK;
    ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBL_SET(pbl);

/* disable separate pbl */
    ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_USP_MASK;

/* descriptor length */
#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MIN_LEN
    ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_ATDS_MASK;
#elif ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN
    ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_ATDS_MASK;
    #endif

/* set the maximum enabled burst length */
    if (ENET_DMA_BUS_MODE_FB_GET(ptr->DMA_BUS_MODE) == 0) {
        ptr->DMA_AXI_MODE |= ENET_DMA_AXI_MODE_BLEN4_MASK | ENET_DMA_AXI_MODE_BLEN8_MASK | ENET_DMA_AXI_MODE_BLEN16_MASK;
    } else {
        /* TODO: set BLENX_MASK */
    }

/* initialize Tx descriptors list: chain mode */
    rt_kprintf("enet_dma_init: enet_dma_tx_desc_chain_init start\r\n");
    enet_dma_tx_desc_chain_init(ptr, desc);

/* initialize Rx descriptors list: Chain Mode  */
    rt_kprintf("enet_dma_init: enet_dma_rx_desc_chain_init start\r\n");
    enet_dma_rx_desc_chain_init(ptr, desc);

rt_kprintf("enet_dma_init: enet_mode_init start\r\n");
    enet_mode_init(ptr, intr);

rt_kprintf("enet_dma_init: enet_dma_flush start\r\n");
    enet_dma_flush(ptr);

return true;
}
```

会卡在`ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)`这一步，置位1之后，硬件会自动复位，但是事实上并没有复位

1 个回答

aozima 2024-12-20

调网络不抓包，调I2C等时序不上逻辑分析仪，就像电工不用万用表！多用整理的好的文字，比截图更省流量，还能在整理过程中思考。

guangxinzhao 2024-12-25

这家伙很懒，什么也没写！

设置的时钟频率是50Mhz，这个我增加了打印，打印输出的均为250Mhz，然后设置网络时钟的时候250/5，IO的是设置完引脚之后直接使用软件导出的，又对比着设计图确认一遍，没问题，但是他还是卡在SWR复位的位置
```
hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
{
	uint32_t clk_freq = 0;
    /* Configure Enet clock to output reference clock */
	if (ptr == HPM_ENET0) {
		if (internal) {
			 /* set pll output frequency at 1GHz */
			if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
				/* set pll2_clk1 output frequence at 250MHz from PLL3 divided by 4 */
				pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 0, 4);
				/* set eth clock frequency at 50MHz for enet0 */
				clock_set_source_divider(clock_eth0, clk_src_pll2_clk0, 5);
				clk_freq = get_frequency_for_source(clk_src_pll2_clk0);
				rt_kprintf("clk_src_pll2_clk0 clk_freq=%d\r\n",clk_freq);
			} else {
				return status_fail;
			}
		}
	} else if (ptr == HPM_ENET1) {
        if (internal) {
        	/* set pll output frequency at 1GHz */
            if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
				/* set pll1_clk1 output frequence at 250MHz from PLL2 divided by 4 */
				pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4);
				/* set eth clock frequency at 50MHz for enet0 */
				clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5);
				clk_freq = get_frequency_for_source(clk_src_pll2_clk1);
				rt_kprintf("clk_src_pll2_clk1 clk_freq=%d\r\n",clk_freq);
			} else {
				return status_fail;
			}
        }
    } else {
        return status_invalid_argument;
    }

enet_rmii_enable_clock(ptr, internal);

return status_success;
}
```c
hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
{
	uint32_t clk_freq = 0;
    /* Configure Enet clock to output reference clock */
	if (ptr == HPM_ENET0) {
		if (internal) {
			 /* set pll output frequency at 1GHz */
			if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
				/* set pll2_clk1 output frequence at 250MHz from PLL3 divided by 4 */
				pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 0, 4);
				/* set eth clock frequency at 50MHz for enet0 */
				clock_set_source_divider(clock_eth0, clk_src_pll2_clk0, 5);
				clk_freq = get_frequency_for_source(clk_src_pll2_clk0);
				rt_kprintf("clk_src_pll2_clk0 clk_freq=%d\r\n",clk_freq);
			} else {
				return status_fail;
			}
		}
	} else if (ptr == HPM_ENET1) {
        if (internal) {
        	/* set pll output frequency at 1GHz */
            if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
				/* set pll1_clk1 output frequence at 250MHz from PLL2 divided by 4 */
				pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4);
				/* set eth clock frequency at 50MHz for enet0 */
				clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5);
				clk_freq = get_frequency_for_source(clk_src_pll2_clk1);
				rt_kprintf("clk_src_pll2_clk1 clk_freq=%d\r\n",clk_freq);
			} else {
				return status_fail;
			}
        }
    } else {
        return status_invalid_argument;
    }

enet_rmii_enable_clock(ptr, internal);

return status_success;
}
```

```c
void init_enet_pins(ENET_Type *ptr)
{
    if (ptr == HPM_ENET0) {
    	HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_GPIO_E_30;
    	HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_ETH0_RXDV;
    	HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_RXD_0;
		HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_RXD_1;
		HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_ETH0_TXEN;
		HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_ETH0_TXD_1;
		HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_ETH0_TXD_0;
		HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_ETH0_REFCLK;
		/*ETH0、ETH1公用*/
		HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC;
		HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO;
		rt_kprintf("init_enet_pins ETH0 init pin\r\n");
/***/
    } else if (ptr == HPM_ENET1) {
    	HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PE29_FUNC_CTL_GPIO_E_29;
        HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV;
        HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0;
        HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1;
        HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN;
        HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0;
        HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1;
        HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_ETH1_REFCLK;
        /*ETH0、ETH1公用*/
        HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC;
		HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO;
		rt_kprintf("init_enet_pins ETH1 init pin\r\n");
/**/
    }
}
```