关于stm32f207 +dp83848平台进行netio测速的问题

发布于 2014-05-11 22:15:41 浏览：3876 订阅该版

1 硬件平台：stm32f207 +dp83848  ，代码使用RTT1.2.0提供的官方例程，修改了ETH的初始化管脚以及开启了硬件校验和，系统能正常ping。采用netio测速的时候结果如下
```
C:Documents and SettingsAdministrator>C:win32-i386.exe -t 192.168.1.30

TCP connection established.
Packet size  1k bytes:  1611 KByte/s Tx,  5231 Byte/s Rx.
Packet size  2k bytes:  1618 KByte/s Tx,  44126 Byte/s Rx.
Packet size  4k bytes:  1620 KByte/s Tx,  31437 Byte/s Rx.
Packet size  8k bytes:  1624 KByte/s Tx,  30768 Byte/s Rx.
Packet size 16k bytes:  1609 KByte/s Tx,  27111 Byte/s Rx.
Packet size 32k bytes:  1635 KByte/s Tx,  25473 Byte/s Rx.
Done.
```

速度明显和aozima大牛在阿莫论坛贴的测速数据不符，远远没有达到芯片的新能。关于LWIP协议栈只修改了
```
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF	4096
/* TCP receive window.*/
#define RT_LWIP_TCP_WND		4096
```
改太大了会出现Rx = -3的打印信息。网络中断处理函数如下
``` 
/* interrupt service routine */
void ETH_IRQHandler(void)
{
    rt_uint32_t status;

/* enter interrupt */
    rt_interrupt_enter();

status = ETH->DMASR;
    
    /* Frame received */
	if ( (status & ETH_DMA_IT_R) != (u32)RESET )
	{
		rt_err_t result;
		/* Clear the interrupt flags. */
		/* Clear the Eth DMA Rx IT pending bits */  
		ETH_DMAClearITPendingBit(ETH_DMA_IT_R);

/* a frame has been received */
		result = eth_device_ready(&(stm32_eth_device.parent));
		if( result != RT_EOK ) rt_kprintf("RX err =%d
", result );
		//RT_ASSERT(result == RT_EOK); 
	}

if ( (status & ETH_DMA_IT_T) != (u32)RESET ) /* packet transmission */
	{
		/*2014.05.10 ????stm32f107?ú????????????????????·?*/
        rt_sem_release(&tx_wait);
        ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
	}

/* Clear received IT */
    if ((status & ETH_DMA_IT_NIS) != (u32)RESET)
        ETH->DMASR = (u32)ETH_DMA_IT_NIS;
    if ((status & ETH_DMA_IT_AIS) != (u32)RESET)
        ETH->DMASR = (u32)ETH_DMA_IT_AIS;
    if ((status & ETH_DMA_IT_RO) != (u32)RESET)
        ETH->DMASR = (u32)ETH_DMA_IT_RO;

/*add*/
    if ((status & ETH_DMA_IT_RBU) != (u32)RESET) 
    {
       ETH_ResumeDMAReception();
       ETH->DMASR = (u32)ETH_DMA_IT_RBU;  
       //rt_kprintf("ETH_DMA_IT_RBU
");        
    }
     
    if ((status & ETH_DMA_IT_TBU) != (u32)RESET) 
    {
       ETH_ResumeDMATransmission();
       ETH->DMASR = (u32)ETH_DMA_IT_TBU;
       //rt_kprintf("ETH_DMA_IT_TBU
");        
    }
    
    /* leave interrupt */
    rt_interrupt_leave();
}
```

网络抓包发现有报文没有ACK
![FastAdmin]()

由于自己对TCP协议实现不熟悉，不知道从何去分析网络收发速度上不去的原因，还请各位懂的大哥多指点指点
![未命名.JPG](https://oss-club.rt-thread.org/uploads/5208_ba2b26e0a9fcb226f2e3134ef05fda99.jpg)

![1.JPG](https://oss-club.rt-thread.org/uploads/5208_fb8c3dce1c0d88a2fdd9e4d1413ae705.jpg)

6 个回答

pangwei 2014-05-11

这家伙很懒，什么也没写！

pangwei 2014-05-11

这家伙很懒，什么也没写！

pangwei 2014-05-11

这家伙很懒，什么也没写！

pangwei 2014-05-11

这家伙很懒，什么也没写！

附上stm32f2_eth.c的代码

```

/*
 * STM32 Eth Driver for RT-Thread
 * Change Logs:
 * Date           Author       Notes
 * 2009-10-05     Bernard      eth interface driver for STM32F107 CL
 */
#include <rtthread.h>
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "stm32f2x7_eth.h"
#include "stm32f2x7_eth_conf.h"
#define CHECKSUM_BY_HARDWARE        1

/*???????¨??1 MAC?????¤×÷??????2 MCO2?±????·????? 3 PHY???????·??·?????*/
#define MII_MODE

#ifdef 	MII_MODE
    /*????MCO2×÷???±??*/
    #define PHY_CLOCK_MOC2
#endif

//#define RMII_MODE  // In this case the System clock frequency is configured
                     // to 100 MHz, for more details refer to system_stm32f2xx.c

#define DP83848_PHY_ADDRESS         0x01 /* Relative to STM322xG-EVAL Board */

#define netifGUARD_BLOCK_TIME       500

/* Ethernet Rx & Tx DMA Descriptors */
extern ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];

/* Ethernet Receive buffers  */
extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];

/* Ethernet Transmit buffers */
extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];

/* Global pointers to track current transmit and receive descriptors */
extern ETH_DMADESCTypeDef  *DMATxDescToSet;
extern ETH_DMADESCTypeDef  *DMARxDescToGet;

/* Global pointer for last received frame infos */
extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;

#define MAX_ADDR_LEN 6
struct rt_stm32_eth
{
	/* inherit from ethernet device */
	struct eth_device parent;

/* interface address info. */
	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
};
static struct rt_stm32_eth stm32_eth_device;
static struct rt_semaphore tx_wait;
/*static rt_bool_t tx_is_waiting = RT_FALSE;*/

static void ETH_MACDMA_Config(void);
static uint32_t ETH_LED_Config(uint16_t PHYAddress);
static uint32_t ETH_Link_ITConfig(uint16_t PHYAddress);

static struct rt_semaphore tx_wait;

/* interrupt service routine */
void ETH_IRQHandler(void)
{
    rt_uint32_t status;

/* enter interrupt */
    rt_interrupt_enter();

/* a frame has been received */
		result = eth_device_ready(&(stm32_eth_device.parent));
		if( result != RT_EOK ) rt_kprintf("RX err =%d
", result );
		//RT_ASSERT(result == RT_EOK); 
	}

/* RT-Thread Device Interface */
/* initialize the interface */
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
	int i;

/* MAC address configuration */
	ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
	
	/* Initialize Tx Descriptors list: Chain Mode */
	ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
	/* Initialize Rx Descriptors list: Chain Mode  */
	ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

/* Enable Ethernet Rx interrrupt */
	{ 
		for(i=0; i<ETH_RXBUFNB; i++)
		{
		  ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
		}
	}
	
	#ifdef CHECKSUM_BY_HARDWARE
	/* Enable the checksum insertion for the Tx frames */
	{
		for(i=0; i<ETH_TXBUFNB; i++)
		{
		  ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
		}
	} 
	#endif

/* Enable MAC and DMA transmission and reception */
	ETH_Start();
    
    return RT_EOK;
}

static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
	return RT_EOK;
}

static rt_err_t rt_stm32_eth_close(rt_device_t dev)
{
	return RT_EOK;
}

static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
	rt_set_errno(-RT_ENOSYS);
	return 0;
}

static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
	rt_set_errno(-RT_ENOSYS);
	return 0;
}

static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
	switch(cmd)
	{
	case NIOCTL_GADDR:
		/* get mac address */
		if(args) memcpy(args, stm32_eth_device.dev_addr, 6);
		else return -RT_ERROR;
		break;

default :
		break;
	}

return RT_EOK;
}

void show_frame(struct pbuf *q)
{
	int i = 0;

char *ptr = q->payload;

for( i = 0; i < q->len; i++ )
	rt_kprintf("0x%02X ", *(ptr++));
	rt_kprintf("
");
}

/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
{
	rt_err_t ret;
	struct pbuf *q;
	uint32_t l = 0;
	u8 *buffer ;
	
	if (( ret = rt_sem_take(&tx_wait, netifGUARD_BLOCK_TIME) ) == RT_EOK)
	{
        buffer =  (u8 *)(DMATxDescToSet->Buffer1Addr);
		for(q = p; q != NULL; q = q->next) 
		{
			/*show_frame(q);*/
			memcpy((u8_t*)&buffer[l], q->payload, q->len);
			l = l + q->len;
		}
		if( ETH_Prepare_Transmit_Descriptors(l) == ETH_ERROR )
			rt_kprintf("Tx Error
");
		rt_sem_release(&tx_wait);
	}
	else
	{
		rt_kprintf("Tx Timeout
");
		return ret;
	}

/* Return SUCCESS */
	return RT_EOK;
}

/* reception packet. */
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
{
	struct pbuf *p, *q;
	u16_t len;
	uint32_t l=0,i =0;
	FrameTypeDef frame;
	u8 *buffer;
	__IO ETH_DMADESCTypeDef *DMARxNextDesc;
	
	p = RT_NULL;
	
	/* Get received frame */
	frame = ETH_Get_Received_Frame_interrupt();
	
	if( frame.length > 0 )
	{
		/* check that frame has no error */
		if ((frame.descriptor->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET)
		{
			//rt_kprintf("Get a frame %d buf = 0x%X, len= %d
", framecnt++, frame.buffer, frame.length);
			/* Obtain the size of the packet and put it into the "len" variable. */
			len = frame.length;
			buffer = (u8 *)frame.buffer;
			
			/* We allocate a pbuf chain of pbufs from the pool. */
			p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
			//p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);

/* Copy received frame from ethernet driver buffer to stack buffer */
			if (p != NULL)
			{ 
			  for (q = p; q != NULL; q = q->next)
			  {
			    memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
			    l = l + q->len;
			  } 
			}
		}
	
		/* Release descriptors to DMA */
		/* Check if received frame with multiple DMA buffer segments */
		if (DMA_RX_FRAME_infos->Seg_Count > 1)
		{
			DMARxNextDesc = DMA_RX_FRAME_infos->FS_Rx_Desc;
		}
		else
		{
			DMARxNextDesc = frame.descriptor;
		}
		
		/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
		for (i=0; i<DMA_RX_FRAME_infos->Seg_Count; i++)
		{  
			DMARxNextDesc->Status = ETH_DMARxDesc_OWN;
			DMARxNextDesc = (ETH_DMADESCTypeDef *)(DMARxNextDesc->Buffer2NextDescAddr);
		}
		
		/* Clear Segment_Count */
		DMA_RX_FRAME_infos->Seg_Count =0;
		
		
		/* When Rx Buffer unavailable flag is set: clear it and resume reception */
		if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)  
		{
			/* Clear RBUS ETHERNET DMA flag */
			ETH->DMASR = ETH_DMASR_RBUS;
			  
			/* Resume DMA reception */
			ETH->DMARPDR = 0;
		}
	}
	return p;
}

static void NVIC_Configuration(void)
{
	NVIC_InitTypeDef NVIC_InitStructure;
    EXTI_InitTypeDef EXTI_InitStructure;
	
	/* 2 bit for pre-emption priority, 2 bits for subpriority */
  	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
	/* Enable the Ethernet global Interrupt */
	NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
	NVIC_Init(&NVIC_InitStructure);

/* Connect EXTI Line to INT Pin */
	SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOB, EXTI_PinSource14);

#if 1
	/* Configure EXTI line */
	EXTI_InitStructure.EXTI_Line = EXTI_Line14;
	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
	EXTI_Init(&EXTI_InitStructure);

/* Enable and set the EXTI interrupt to the highest priority */
	NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
	NVIC_Init(&NVIC_InitStructure);
    #endif
}

/*
 * GPIO Configuration for ETH
 */
static void GPIO_Configuration(void)
{

GPIO_InitTypeDef GPIO_InitStructure;
  
	/* Enable GPIOs clocks */
	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC |
												 RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG, ENABLE);
	/* Enable SYSCFG clock */
	RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);  
  
	/* MII/RMII Media interface selection --------------------------------------*/
#ifdef MII_MODE
	#ifdef PHY_CLOCK_MCO1
	/* Configure MCO1 (PA8) */
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	/*GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;*/
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;	
	GPIO_Init(GPIOA, &GPIO_InitStructure);
	
	GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_MCO);
  
	/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
	RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
	#endif
  
	#ifdef PHY_CLOCK_MOC2
	//Configure MCO2 (PC9)
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;  
	GPIO_Init(GPIOC, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOC,GPIO_PinSource9,GPIO_AF_MCO);
	//Output HSE clock(25MHz) on MCO2 pin(PC9) to clock the PHY
	RCC_MCO2Config(RCC_MCO2Source_HSE,RCC_MCO2Div_1);
	#endif /* PHY_CLOCK_MCO */

SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
#elif defined RMII_MODE  /* Mode RMII with STM322xG-EVAL */

SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
#endif

/* Ethernet pins configuration ************************************************/
   /*
					
											LQFP176				LQFP144			UFBGA176
        ETH_MII_CRS ----------------------> PA0					PH2
		ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
		ETH_MDIO -------------------------> PA2
        ETH_MII_COL ----------------------> PA3					PH3
		ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
		ETH_MII_RXD2 ---------------------> PB0					PH6
		ETH_MII_RXD3 ---------------------> PB1					PH7
		ETH_MII_TXD3 ---------------------> PB8
		ETH_MII_RX_ER --------------------> PB10				PI10
		ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12
		ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13
		ETH_MDC --------------------------> PC1
        ETH_MII_TXD2 ---------------------> PC2
        ETH_MII_TX_CLK -------------------> PC3
        ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
        ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5       
        ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11
        
        ??????????
		PHY_RESET ------------------------> PB11
		PHY_PWR/INT ----------------------> PF9
                                                  */
	/* Configure PA0, PA1, PA2 and PA7 */
	GPIO_InitStructure.GPIO_Pin 	=GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode 	= GPIO_Mode_AF;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	GPIO_InitStructure.GPIO_PuPd 	= GPIO_PuPd_NOPULL ;
	GPIO_Init(GPIOA, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_ETH);//PA0=ETH_MII_CRS
	GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH);//PA3=ETH_MII_COL
	GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);

/* ConfigurePB0, PB1, PB5, PB10, PB12 and PB13 */
	GPIO_InitStructure.GPIO_Pin =GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_10 | GPIO_Pin_12 | GPIO_Pin_13;
	GPIO_Init(GPIOB, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);

/* Configure PC1, PC2, PC3, PC4 and PC5 */
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
	GPIO_Init(GPIOC, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
	GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
  
	/* Configure PE2 */
	/*GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
	GPIO_Init(GPIOE, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOE, GPIO_PinSource2, GPIO_AF_ETH);//ETH_MII_TXD3
	*/	
	/* Configure PG11 */
	GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11;
	GPIO_Init(GPIOG, &GPIO_InitStructure);
	GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);

/*??PB7 PB11??????IO????*/
	/*GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN ;//PHY_TX_ER
	GPIO_Init(GPIOB,&GPIO_InitStructure);
	*/	
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;//PHY_RESET
	GPIO_Init(GPIOB,&GPIO_InitStructure);
	/* Configure PF9 */
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;//PHY_PWR/INT
	GPIO_Init(GPIOF,&GPIO_InitStructure);

/* Configure INT pin as input */
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
	GPIO_Init(GPIOB, &GPIO_InitStructure);
    
	GPIO_SetBits(GPIOF,GPIO_Pin_9);
	GPIO_ResetBits(GPIOB,GPIO_Pin_11);//????PHY
    rt_thread_delay(1);
    GPIO_SetBits(GPIOB,GPIO_Pin_11);//????PHY
}

/*????PHY LED????*/
static uint32_t ETH_LED_Config(uint16_t PHYAddress)
{
	uint16_t tmpreg = 0;	
	
	/*????LED??????mode 3*/
	tmpreg = ETH_ReadPHYRegister(PHYAddress,PHY_CR);
	tmpreg |= (uint16_t)(PHY_CR_LED_CNFG1);
	tmpreg &= (uint16_t)~(PHY_CR_LED_CNFG0);
	
	if(!(ETH_WritePHYRegister(PHYAddress, PHY_CR, tmpreg)))
	{
		/* Return ERROR in case of write timeout */
		return ETH_ERROR;
	}

return ETH_SUCCESS;
}

__attribute__((unused)) static uint32_t ETH_Link_ITConfig(uint16_t PHYAddress)
{
  uint32_t tmpreg = 0;

/* Read MICR register */
  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MICR);

/* Enable output interrupt events to signal via the INT pin */
  tmpreg |= (uint32_t)PHY_MICR_INT_EN | PHY_MICR_INT_OE;
  if(!(ETH_WritePHYRegister(PHYAddress, PHY_MICR, tmpreg)))
  {
    /* Return ERROR in case of write timeout */
    return ETH_ERROR;
  }
	
  /* Read MISR register */
  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MISR);

/* Enable Interrupt on change of link status */
  tmpreg |= (uint32_t)PHY_MISR_LINK_INT_EN;
  if(!(ETH_WritePHYRegister(PHYAddress, PHY_MISR, tmpreg)))
  {
    /* Return ERROR in case of write timeout */
    return ETH_ERROR;
  }

return ETH_SUCCESS;   
}

/**
  * @brief  Configures the Ethernet Interface
  * @param  None
  * @retval None
  */
static void ETH_MACDMA_Config(void)
{
  ETH_InitTypeDef ETH_InitStructure;

/* Enable ETHERNET clock  */
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
                        RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
                        
  /* Reset ETHERNET on AHB Bus */
  ETH_DeInit();

/* Software reset */
  ETH_SoftwareReset();

/* Wait for software reset */
  while (ETH_GetSoftwareResetStatus() == SET);

/* ETHERNET Configuration --------------------------------------------------*/
  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
  ETH_StructInit(Ð_InitStructure);

/* Fill ETH_InitStructure parametrs */
  /*------------------------   MAC   -----------------------------------*/
  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
  //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; 
  //  ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
  //  ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;

ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
#ifdef CHECKSUM_BY_HARDWARE
  ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif

/*------------------------   DMA   -----------------------------------*/  
  
  /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 
  the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 
  if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
  ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; 
  ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         
  ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
 
  ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
  ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   
  ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
  ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      
  ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                
  ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          
  ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
  ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;

/* Configure Ethernet */
  if( ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS) ==  ETH_ERROR )
  	rt_kprintf("ETH init error, may be no link
");

/* Enable the Ethernet Rx Interrupt */
  ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE);
}

void Eth_Link_ITHandler(uint16_t PHYAddress)
{
  /* Check whether the link interrupt has occurred or not */
  if(((ETH_ReadPHYRegister(PHYAddress, PHY_MISR)) & PHY_LINK_STATUS) != 0)
  {
        rt_kprintf("Eth_Link_ITHandler
");
  }
}

void EXTI15_10_IRQHandler(void)
{
  rt_kprintf("EXTI15_10_IRQHandler
");
 
  if(EXTI_GetITStatus(EXTI_Line14) != RESET)
  {
       Eth_Link_ITHandler(DP83848_PHY_ADDRESS);
       /* Clear interrupt pending bit */
       EXTI_ClearITPendingBit(EXTI_Line14);
  }
}

#define   DevID_SNo0       (*((rt_uint32_t *)0x1FFF7A10));  
#define   DevID_SNo1       (*((rt_uint32_t *)0x1FFF7A10+32));  
#define   DevID_SNo2       (*((rt_uint32_t *)0x1FFF7A10+64));

void rt_hw_stm32_eth_init(void)
{
	GPIO_Configuration();
	NVIC_Configuration();
	ETH_MACDMA_Config();
	
    ETH_LED_Config(DP83848_PHY_ADDRESS);
    
    /*???????????????ì????????????°???*/
    ETH_Link_ITConfig(DP83848_PHY_ADDRESS);
	
    
    stm32_eth_device.dev_addr[0] = 0x00;
    stm32_eth_device.dev_addr[1] = 0x60;
    stm32_eth_device.dev_addr[2] = 0x6e;
	{
		uint32_t cpu_id[3] = {0};
		cpu_id[2] = DevID_SNo2; cpu_id[1] = DevID_SNo1; cpu_id[0] = DevID_SNo0;
		
		// generate MAC addr from 96bit unique ID (only for test)
		stm32_eth_device.dev_addr[3] = (uint8_t)((cpu_id[0]>>16)&0xFF);
	    stm32_eth_device.dev_addr[4] = (uint8_t)((cpu_id[0]>>8)&0xFF);
	    stm32_eth_device.dev_addr[5] = (uint8_t)(cpu_id[0]&0xFF);

//	    stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
//	    stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
//	    stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
	}

stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
	stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
	stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
	stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
	stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
	stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
	stm32_eth_device.parent.parent.user_data  = RT_NULL;

stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
	stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;

/* init tx semaphore */
	rt_sem_init(&tx_wait, "tx_wait", 1, RT_IPC_FLAG_FIFO);

/* register eth device */
	eth_device_init(&(stm32_eth_device.parent), "e0");
}

static char led = 0;

void dp83483()
{
	uint16_t bsr,sts, bcr, phycr;

bsr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR);
	sts = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
	bcr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BCR);
	phycr = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);

rt_kprintf("BCR = 0x%X	BSR = 0x%X	PHY_STS = 0x%X	PHY_CR = 0x%X
", bcr,bsr,sts, phycr);

rt_kprintf("PHY_FCSCR = 0x%X
", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_FCSCR	) );
	rt_kprintf("PHY_MISR = 0x%X
", ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_MISR ) );

rt_kprintf("DMASR = 0x%X
", ETH->DMASR );

//ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_LEDCR, (uint16_t)(0x38 | led));
	led = (led==7)?0:7;

}
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT(dp83483, Show PHY register.);
#endif

```

其中stm32f2x7_eth.c为st官方的
/**
  ******************************************************************************
  * @file    stm32f2x7_eth.c
  * @author  MCD Application Team
  * @version V1.0.0
  * @date    25-April-2011
  * @brief   This file is the low level driver for STM32F2x7 Ethernet Controller.
  *          This driver does not include low level functions for PTP time-stamp.            
  ******************************************************************************