中断延迟硬实时 EtherCAT

请教如何优化关闭中断时间

发布于 2019-01-17 14:18:41 浏览：3292 订阅该版

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moss 2019-01-18

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gpfrank 2019-01-20

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moss 2019-01-21

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gpfrank 2019-01-21

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bear1 2019-09-16

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bear1 2019-09-16

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Cortex-M3/4 Implementation

Such high priority, nested interrupt handler has been implemented for the Cortex-M3/4 families. The following paragraphs will summarize that implementation.
Configuration Options
CONFIG_ARCH_HIPRI_INTERRUPT

If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most interrupts will not have execution priority. SVCall must have execution priority in all cases.

In the normal cases, interrupts are not nest-able and all interrupts run at an execution priority between NVIC_SYSH_PRIORITY_MIN and NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).

If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special high priority interrupts are supported. These are not “nested” in the normal sense of the word. These high priority interrupts can interrupt normal processing but execute outside of OS (although they can “get back into the game” via a PendSV interrupt).