RTT Nano内存泄漏问题

发布于 2022-01-05 11:14:55 浏览：1151 订阅该版

4 个回答

youshenmebutuo 2022-01-05

这家伙很懒，什么也没写！

QTWH_4470 2022-01-05

这家伙很懒，什么也没写！

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NOUSED 2022-01-05

这家伙很懒，什么也没写！

QTWH_4470 2022-01-05

这家伙很懒，什么也没写！

NOUSED 2022-01-05

这家伙很懒，什么也没写！

QTWH_4470 2022-01-05

这家伙很懒，什么也没写！

QTWH_4470 2022-01-05

这家伙很懒，什么也没写！

NOUSED 2022-01-05

这家伙很懒，什么也没写！

NOUSED 2022-01-05

这家伙很懒，什么也没写！

@QTWH_4470 `SystemCoreClock = 168000000` 相当于手动初始化了。

实际上即便是裸机，`SystemInit` 都是一些配置寄存器的操作，即使读全局变量，也要先手动初始化，不会上来就直接读的

```c
/**
  * @brief  Setup the microcontroller system
  *         Initialize the Embedded Flash Interface, the PLL and update the 
  *         SystemCoreClock variable.
  * @note   This function should be used only after reset.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
  RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
  RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
  /* Reset PLL2ON and PLL3ON bits */
  RCC->CR &= (uint32_t)0xEBFFFFFF;

/* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x00FF0000;

/* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;

/* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
    
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
  #ifdef DATA_IN_ExtSRAM
    SystemInit_ExtMemCtl(); 
  #endif /* DATA_IN_ExtSRAM */
#endif

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
  /* Configure the Flash Latency cycles and enable prefetch buffer */
  SetSysClock();

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif 
}
```