RT-Thread-一个不知是什么问题导致的系统溃了！RT-Thread问答社区

一个不知是什么问题导致的系统溃了！

发布于 2012-12-25 15:31:18 浏览：4406 订阅该版

正常运行的时候，动态线程的状态情况如图注意那个地址。。图一的地址是出现问题后的地址。
系统崩溃前: 动态线 phytid 指针 0x68000D8C
系统崩溃后: 动态线 phytid 指针 0x68000D8C

phytid指针指向地址没改变, 只是phytid指针结构体数据乱了

但是在这个 0x68000C42 地址中找到了 phytid 结构体数据, 
初步判断数据是正确的.

结论: phytid 结构体数据从 0x68000D8C 被搬移到 0x68000C42
全局变量
rt_thread_t phytid;原地址应该是0x68000d8c
![11.jpg](/uploads/3459_4e698b452659260e53f071aa43bc5afd.jpg)
系统崩溃后，动态线程的状态情况如图
![2-命名工程.png](/uploads/5191_9848c0fc7118f82a9baf5e046cfdb0f8.png)
但是之后我看了一下MEMROY里面的数据。我发现我动态线程的状态数据保存到了另一个地址里面跟原来的地址不一样如图三。
![3-选择模板.png](/uploads/5191_dfd114e10225b873782d51cd9ab0946d.png)
。状态都还是
还跟原来是一样的比如原来是在0x68000d8c如图1,线程状态保存到了0x68000c42如图2，但是我的动态线程指针还是指向0x68000d8c所以系统崩溃了
崩溃
![4-主界面.png](/uploads/5191_b889c0f9aea41120f85a29db52674307.png)
这个是长时间运行之后才出现的问题。。已经运行了一天半了。。不是一时半会就出现的问题。。
系统就是一直从网络上面接收shoutcast电台的数据。。电台是我自己建的。。就是局域网内
工程是
ealtouch-stm32f4-master应该是9月3号那个版本
RTT版本为1.10自己下载的
MDK是4。23的
JLINK驱动4.36l 
SRAM配置以下IS61WV102416BLL
主芯片stm32f407
网络芯片DP83848
MP3解码芯片VS1003

```
void ext_sram_init(void)
{
    FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
    FSMC_NORSRAMTimingInitTypeDef  Timing_read,Timing_write;

FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &Timing_read;
    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &Timing_write;

FSMC_NORSRAMStructInit(&FSMC_NORSRAMInitStructure);

/*--------------------- read timings configuration ---------------------*/
    Timing_read.FSMC_AddressSetupTime = 2;  /* [3:0] F2/F4 1~15 HCLK */
    Timing_read.FSMC_AddressHoldTime = 0;   /* [7:4] keep 0x00 in SRAM mode */
    Timing_read.FSMC_DataSetupTime = 3;     /* [15:8] F2/F4 0~255 HCLK */
    /* [19:16] Time between NEx high to NEx low (BUSTURN HCLK) */
    Timing_read.FSMC_BusTurnAroundDuration = 1;
    Timing_read.FSMC_CLKDivision = 0; /* [24:20] keep 0x00 in SRAM mode  */
    Timing_read.FSMC_DataLatency = 0; /* [27:25] keep 0x00 in SRAM mode  */
    Timing_read.FSMC_AccessMode = FSMC_AccessMode_A;

/*--------------------- write timings configuration ---------------------*/
    Timing_write.FSMC_AddressSetupTime = 2;  /* [3:0] F2/F4 1~15 HCLK */
    Timing_write.FSMC_AddressHoldTime = 0;   /* [7:4] keep 0x00 in SRAM mode */
    Timing_write.FSMC_DataSetupTime = 3;     /* [15:8] F2/F4 0~255 HCLK */
    /* [19:16] Time between NEx high to NEx low (BUSTURN HCLK) */
    Timing_write.FSMC_BusTurnAroundDuration = 1;
    Timing_write.FSMC_CLKDivision = 0; /* [24:20] keep 0x00 in SRAM mode  */
    Timing_write.FSMC_DataLatency = 0; /* [27:25] keep 0x00 in SRAM mode  */
    Timing_write.FSMC_AccessMode = FSMC_AccessMode_A;   /* FSMC 访问模式 */

/* Reset NOR/SRAM Init structure parameters values */
//  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
//  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
//  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
//  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
//  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
//  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
//  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
//  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
//  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
//  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
//  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
//  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
//  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;

/*-------------------------- SRAM configuration --------------------------*/
    FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
    FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
    FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
    FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
    FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
    FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
    FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
    FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
    FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
    FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
    FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
    FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

/*------------------------------ SRAM init ------------------------------*/
    FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
    FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
    FSMC_NORSRAMCmd(FSMC_NORSRAMInitStructure.FSMC_Bank, ENABLE);
}

{
phytid = rt_thread_create("phy",
                               phy_monitor_thread_entry,
                               RT_NULL,
                               512,
                               RT_THREAD_PRIORITY_MAX - 2,
                               2);
if (phytid != RT_NULL)
      rt_thread_startup(phytid);
}
/* PHY: LAN8720 */
static uint8_t phy_speed = 0;
#define PHY_LINK_MASK       (1<<0)
#define PHY_100M_MASK       (1<<1)
#define PHY_DUPLEX_MASK     (1<<2)
static void phy_monitor_thread_entry(void *parameter)
{
    uint8_t phy_addr = 0xFF;
    uint8_t phy_speed_new = 0;
	uint16_t status;
	uint16_t SR;	 
    /* phy search */
    {
        rt_uint32_t i;
        rt_uint16_t temp;

for(i=0; i<=0x1F; i++)
        {
            temp = ETH_ReadPHYRegister(i, 0x02);

if( temp != 0xFFFF )
            {
                phy_addr = i;
                break;
            }
        }
    } /* phy search */

if(phy_addr == 0xFF)
    {
        STM32_ETH_PRINTF("phy not probe!
");
        return;
    }
    else
    {
        STM32_ETH_PRINTF("found a phy, address:0x%02X
", phy_addr);
    }

/* RESET PHY */
    STM32_ETH_PRINTF("RESET PHY!
");
    ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
    rt_thread_delay(RT_TICK_PER_SECOND * 2);
    ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);

while(1)
    {
        status  = ETH_ReadPHYRegister(phy_addr, PHY_BSR);
        STM32_ETH_PRINTF("LAN8720 status:0x%04X
", status);

phy_speed_new = 0;

if(status & (PHY_AutoNego_Complete | PHY_Linked_Status))
        {

SR = ETH_ReadPHYRegister(phy_addr, 31);
            STM32_ETH_PRINTF("LAN8720 REG 31:0x%04X
", SR);

SR = (SR >> 2) & 0x07; /* LAN8720, REG31[4:2], Speed Indication. */
            phy_speed_new = PHY_LINK_MASK;

if((SR & 0x03) == 2)
            {
                phy_speed_new |= PHY_100M_MASK;
            }

if(SR & 0x04)
            {
                phy_speed_new |= PHY_DUPLEX_MASK;
            }
        }

/* linkchange */
        if(phy_speed_new != phy_speed)
        {
            if(phy_speed_new & PHY_LINK_MASK)
            {
                STM32_ETH_PRINTF("link up ");

if(phy_speed_new & PHY_100M_MASK)
                {
                    STM32_ETH_PRINTF("100Mbps");
                    stm32_eth_device.ETH_Speed = ETH_Speed_100M;
                }
                else
                {
                    stm32_eth_device.ETH_Speed = ETH_Speed_10M;
                    STM32_ETH_PRINTF("10Mbps");
                }

if(phy_speed_new & PHY_DUPLEX_MASK)
                {
                    STM32_ETH_PRINTF(" full-duplex
");
                    stm32_eth_device.ETH_Mode = ETH_Mode_FullDuplex;
                }
                else
                {
                    STM32_ETH_PRINTF(" half-duplex
");
                    stm32_eth_device.ETH_Mode = ETH_Mode_HalfDuplex;
                }
                rt_stm32_eth_init((rt_device_t)&stm32_eth_device);

/* send link up. */
                eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
            } /* link up. */
            else
            {
                STM32_ETH_PRINTF("link down
");
                /* send link down. */
                eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
            } /* link down. */

phy_speed = phy_speed_new;
        } /* linkchange */

rt_thread_delay(RT_TICK_PER_SECOND);
    } /* while(1) */
}
```
![22.jpg](https://oss-club.rt-thread.org/uploads/3459_7d211c12bca0d9eba131b7dc782bbf4b.jpg)

![33.jpg](https://oss-club.rt-thread.org/uploads/3459_79ac68eaa2339095e07de000788407f2.jpg)

![44.jpg](https://oss-club.rt-thread.org/uploads/3459_4cb93836ce8fe24e9058cbdec5383774.jpg)