求助rt-smart在适配riscv64虚拟地址和物理地址映射关系

发布于 2023-02-15 16:10:24 浏览：874 订阅该版

在bl808适配RT-THREAD master分支上的rt-smart过程中，遇到了虚拟地址和物理地址映射问题，寻求熟悉rt-smart的大佬帮助

BL808使用的是平头哥C906的RISC-V内核

1、当前在未开启`RT_USING_SMART`宏情况下，系统可以在物理地址上正常运行，任务切换正常。
内存物理地址：`0x50000000`，大小64MByte
链接地址：`0x50000000`
PLIC物理地址：`0xe0000000`

在启动的时候，boot负责将rtthread这部分代码搬移到内存`0x50000000`。

2、在bsp下开启`RT_USING_SMART`选项，参考`allwinner/d1s`下的配置，
（1）修改配置`rtconfig.h`为

```c
#define KERNEL_VADDR_START 0x50000000
#define PV_OFFSET 0x0
```

（2）在rt_hw_board_init函数中添加
```c
#ifdef RT_USING_SMART
    rt_hw_mmu_map_init(&rt_kernel_space, (void *)(USER_VADDR_START - IOREMAP_SIZE), IOREMAP_SIZE, (rt_size_t *)MMUTable, 0);
    rt_page_init(init_page_region);
    rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, NUM_MEM_DESC);
#endif

struct mem_desc platform_mem_desc[] = {
    {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x4000000 - 1, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM},
    {0x1000, 0x4ffff000 - 1, 0x1000 + PV_OFFSET, DEVICE_MEM},
};
```

基于以上配置的情况下，RT-SMART宏开启后，写plic之后就会发生异常，

```
Unhandled Exception 7:Store/AMO Access Fault
scause:0x0000000000000007,stval:0x0000000010201000,sepc:0x00000000500248b4
--------------Dump Registers-----------------
Function Registers:
        ra(x1) = 0x0000000050024cca     user_sp = 0x000000005003f840
        gp(x3) = 0x000000005003c0a0     tp(x4) = 0x0000000000000000
Temporary Registers:
        t0(x5) = 0x0000000000004000     t1(x6) = 0x0000000000000000
        t2(x7) = 0x0000000000000001
        t3(x28) = 0x0000000000000000    t4(x29) = 0x0000000000000000
        t5(x30) = 0x0000000000000000    t6(x31) = 0x0000000000000000
Saved Registers:
        s0/fp(x8) = 0x000000005003f860  s1(x9) = 0x0000000000000000
        s2(x18) = 0x0000000000000000    s3(x19) = 0x0000000000000000
        s4(x20) = 0x0000000000000000    s5(x21) = 0x0000000000000000
        s6(x22) = 0x0000000000000000    s7(x23) = 0x0000000000000000
        s8(x24) = 0x0000000000000000    s9(x25) = 0x0000000000000000
        s10(x26) = 0x0000000000000000   s11(x27) = 0x0000000000000000
Function Arguments Registers:
        a0(x10) = 0x0000000000000000    a1(x11) = 0x0000000010201000
        a2(x12) = 0x0000000000000004    a3(x13) = 0x0000000000000080
        a4(x14) = 0x0000000000000000    a5(x15) = 0x0000000010201000
        a6(x16) = 0xfefefefefefefeff    a7(x17) = 0x0000000000000007
sstatus = 0x0000000200040100
        Supervisor Interrupt Disabled
        Last Time Supervisor Interrupt Disabled
        Last Privilege is Supervisor Mode
        Permit to Access User Page
        Not Permit to Read Executable-only Page
satp = 0x800000000005006f
        Current Page Table(Physical) = 0x000000005006f000
        Current ASID = 0x0000000000000000
        Mode = Page-based 39-bit Virtual Addressing Mode
-----------------Dump OK---------------------
--------------Thread list--------------
current thread: (NULL)
--------------Backtrace--------------
riscv64-unknown-linux-musl-addr2line -e rtthread.elf -a -f 00000000500248b0
```

目前关于RT-SMART的资料较少，官网文档中心里面讲的也不是特别详细，想寻求一下大佬支持，谢谢

3 个回答

xiaorui 认证专家 2023-02-15

小睿手办 https://item.taobao.com/item.htm?id=674889867009

GuEe_GUI 2023-02-15

这家伙很懒，什么也没写！

aozima 2023-02-15

调网络不抓包，调I2C等时序不上逻辑分析仪，就像电工不用万用表！多用整理的好的文字，比截图更省流量，还能在整理过程中思考。

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追加回复

燕十三 2023-02-15

这家伙很懒，什么也没写！

这部分代码在D1S开启MMU之后也是可以正常使用的。
在BL808没有开启MMU也是可以正常使用的，所以我怀疑是不是虚拟地址和物理地址转换没有处理好
在运行
`writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);`
这句话就异常了

```c
void plic_init(void)
{
    int nr_irqs;
    int nr_context;
    int i;
    unsigned long hwirq;
    int cpu = 0;

if (c906_plic_regs)
    {
        LOG_E("plic already initialized!");
        return;
    }

nr_context = C906_NR_CONTEXT;

c906_plic_regs = (void *)C906_PLIC_PHY_ADDR;
    if (!c906_plic_regs)
    {
        LOG_E("fatal error, plic is reg space is null.");
        return;
    }

nr_irqs = C906_PLIC_NR_EXT_IRQS;

for (i = 0; i < nr_context; i ++)
    {
        struct plic_handler *handler;
        uint32_t threshold = 0;

cpu = 0;

/* skip contexts other than supervisor external interrupt */
        if (i == 0)
        {
            continue;
        }

// we always use CPU0 M-mode target register.
        handler = &c906_plic_handlers[cpu];
        if (handler->present)
        {
            threshold  = 0xffffffff;
            goto done;
        }

handler->present = RT_TRUE;
        handler->hart_base = c906_plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
        handler->enable_base = c906_plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
done:
        /* priority must be > threshold to trigger an interrupt */
        writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
        for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
        {
            plic_toggle(handler, hwirq, 0);
        }
    }

/* Enable supervisor external interrupts. */
    set_csr(sie, SIE_SEIE);
}

```